Skip to content

Commit 2d77615

Browse files
jacobly0jacobly0
committed
Fix instruction names that can't take index half registers.
1 parent 48fb58e commit 2d77615

File tree

6 files changed

+172
-168
lines changed

6 files changed

+172
-168
lines changed

‎llvm/lib/Target/Z80/GISel/Z80InstructionSelector.cpp

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -492,7 +492,7 @@ bool Z80InstructionSelector::selectSExt(MachineInstr &I,
492492
}
493493

494494
MachineIRBuilder MIB(I);
495-
auto Rotate = MIB.buildInstr(Z80::RRC8r, {LLT::scalar(8)}, {SrcReg});
495+
auto Rotate = MIB.buildInstr(Z80::RRC8g, {LLT::scalar(8)}, {SrcReg});
496496
if (!constrainSelectedInstRegOperands(*Rotate, TII, TRI, RBI))
497497
return false;
498498
auto Fill = MIB.buildInstr(FillOpc);
@@ -1120,7 +1120,7 @@ bool Z80InstructionSelector::selectMergeValues(MachineInstr &I,
11201120
RC = &Z80::R24RegClass;
11211121
Register UpReg = I.getOperand(3).getReg(), TmpReg;
11221122
if (mi_match(UpReg, MRI, m_GAShr(m_Reg(TmpReg), m_SpecificICst(7)))) {
1123-
auto AddI = MIB.buildInstr(Z80::RLC8r, {LLT::scalar(8)}, {TmpReg});
1123+
auto AddI = MIB.buildInstr(Z80::RLC8g, {LLT::scalar(8)}, {TmpReg});
11241124
auto SbcI = MIB.buildInstr(Z80::SBC24aa);
11251125
SbcI->findRegisterUseOperand(Z80::UHL)->setIsUndef();
11261126
TmpReg = MIB.buildCopy(RC, Register(Z80::UHL)).getReg(0);
@@ -1400,7 +1400,7 @@ Z80::CondCode Z80InstructionSelector::foldExtendedAddSub(
14001400
auto SetCC = MIB.buildInstr(Z80::SetCC, {LLT::scalar(1)}, {int64_t(CC)});
14011401
if (!RBI.constrainGenericRegister(SetCC.getReg(0), Z80::R8RegClass, MRI))
14021402
return Z80::COND_INVALID;
1403-
auto BitI = MIB.buildInstr(Z80::RRC8r, {LLT::scalar(8)}, {SetCC});
1403+
auto BitI = MIB.buildInstr(Z80::RRC8g, {LLT::scalar(8)}, {SetCC});
14041404
if (!constrainSelectedInstRegOperands(*BitI, TII, TRI, RBI))
14051405
return Z80::COND_INVALID;
14061406
if (!select(*SetCC))
@@ -1572,7 +1572,7 @@ Z80InstructionSelector::foldCond(Register CondReg, MachineIRBuilder &MIB,
15721572
case Z80::COND_C:
15731573
case Z80::COND_M: {
15741574
CondRC = selectRRegClass(CondReg, MRI);
1575-
auto RotateI = MIB.buildInstr(Z80::RRC8r, {s1}, {CondReg});
1575+
auto RotateI = MIB.buildInstr(Z80::RRC8g, {s1}, {CondReg});
15761576
if (CondRC != &Z80::R8RegClass)
15771577
RotateI->getOperand(1).setSubReg(Z80::sub_low);
15781578
if (!constrainSelectedInstRegOperands(*RotateI, TII, TRI, RBI))
@@ -1613,7 +1613,7 @@ bool Z80InstructionSelector::selectShift(MachineInstr &I,
16131613
llvm_unreachable("Illegal type");
16141614
case 8:
16151615
Reg = Z80::A;
1616-
AddOpc = Z80::RLC8r;
1616+
AddOpc = Z80::RLC8g;
16171617
SbcOpc = Z80::SBC8ar;
16181618
RC = &Z80::R8RegClass;
16191619
break;
@@ -1679,11 +1679,11 @@ bool Z80InstructionSelector::selectFunnelShift(MachineInstr &I,
16791679
MachineIRBuilder MIB(I);
16801680
while (Count--) {
16811681
auto ShiftI = MIB.buildInstr(
1682-
IsLeft ? Z80::RLC8r : Z80::RRC8r,
1682+
IsLeft ? Z80::RLC8g : Z80::RRC8g,
16831683
{Count || HiReg != LoReg ? DstOp{Ty} : DstOp{DstReg}}, {HiReg});
16841684
MachineInstrBuilder RotateI;
16851685
if (HiReg != LoReg)
1686-
RotateI = MIB.buildInstr(IsLeft ? Z80::RL8r : Z80::RR8r,
1686+
RotateI = MIB.buildInstr(IsLeft ? Z80::RL8g : Z80::RR8g,
16871687
{Count ? DstOp{Ty} : DstOp{DstReg}}, {LoReg});
16881688
if (!constrainSelectedInstRegOperands(*ShiftI, TII, TRI, RBI) ||
16891689
(HiReg != LoReg &&

‎llvm/lib/Target/Z80/Z80InstrInfo.cpp

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -1514,7 +1514,7 @@ bool Z80InstrInfo::analyzeCompare(const MachineInstr &MI, Register &SrcReg,
15141514
switch (MI.getOpcode()) {
15151515
default: return false;
15161516
case Z80::OR8ar:
1517-
case Z80::TST8ar:
1517+
case Z80::TST8ag:
15181518
SrcReg = Z80::A;
15191519
if (MI.getOperand(1).getReg() != SrcReg)
15201520
return false;
@@ -1590,16 +1590,16 @@ inline static bool isSZSettingInstr(MachineInstr &MI) {
15901590
case Z80::AND8ar: case Z80::AND8ai: case Z80::AND8ap: case Z80::AND8ao:
15911591
case Z80::XOR8ar: case Z80::XOR8ai: case Z80::XOR8ap: case Z80::XOR8ao:
15921592
case Z80:: OR8ar: case Z80:: OR8ai: case Z80:: OR8ap: case Z80:: OR8ao:
1593-
case Z80::TST8ar: case Z80::TST8ai: case Z80::TST8ap:
1593+
case Z80::TST8ag: case Z80::TST8ai: case Z80::TST8ap:
15941594
case Z80::SBC16ao:case Z80::NEG: case Z80::ADC16ao:
15951595
case Z80::SUB16ao:case Z80::SUB24ao:
1596-
case Z80::RLC8r: case Z80::RLC8p: case Z80::RLC8o:
1597-
case Z80::RRC8r: case Z80::RRC8p: case Z80::RRC8o:
1598-
case Z80:: RL8r: case Z80:: RL8p: case Z80:: RL8o:
1599-
case Z80:: RR8r: case Z80:: RR8p: case Z80:: RR8o:
1600-
case Z80::SLA8r: case Z80::SLA8p: case Z80::SLA8o:
1601-
case Z80::SRA8r: case Z80::SRA8p: case Z80::SRA8o:
1602-
case Z80::SRL8r: case Z80::SRL8p: case Z80::SRL8o:
1596+
case Z80::RLC8g: case Z80::RLC8p: case Z80::RLC8o:
1597+
case Z80::RRC8g: case Z80::RRC8p: case Z80::RRC8o:
1598+
case Z80:: RL8g: case Z80:: RL8p: case Z80:: RL8o:
1599+
case Z80:: RR8g: case Z80:: RR8p: case Z80:: RR8o:
1600+
case Z80::SLA8g: case Z80::SLA8p: case Z80::SLA8o:
1601+
case Z80::SRA8g: case Z80::SRA8p: case Z80::SRA8o:
1602+
case Z80::SRL8g: case Z80::SRL8p: case Z80::SRL8o:
16031603
return true;
16041604
}
16051605
}
@@ -1883,7 +1883,7 @@ MachineInstr *Z80InstrInfo::foldMemoryOperandImpl(
18831883
case Z80::AND8ar: Opc = IsOff ? Z80::AND8ao : Z80::AND8ap; break;
18841884
case Z80::XOR8ar: Opc = IsOff ? Z80::XOR8ao : Z80::XOR8ap; break;
18851885
case Z80:: OR8ar: Opc = IsOff ? Z80:: OR8ao : Z80:: OR8ap; break;
1886-
case Z80::TST8ar:
1886+
case Z80::TST8ag:
18871887
if (IsOff)
18881888
return nullptr;
18891889
Opc = Z80::TST8ap;

‎llvm/lib/Target/Z80/Z80InstrInfo.td

Lines changed: 57 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -714,59 +714,61 @@ let mayLoad = true, mayStore = true in {
714714
let Defs = [F] in
715715
multiclass UnOp8RF<OtherPrefix prefix, bits<8> opcode, string mnemonic,
716716
list<Predicate> Preds = []> {
717-
defvar rc8 = !if(!eq(prefix, CBPre), G8, R8);
718-
def 8r : I <Pre<Idx0Pre, prefix>, opcode, mnemonic, "\t$dst", "$imp = $dst",
719-
(outs rc8:$dst), (ins rc8:$imp),
720-
[(set rc8:$dst, F,
721-
(!cast<SDNode>(!strconcat("Z80", mnemonic, "_flag"))
722-
rc8:$imp))]>,
723-
Requires<Preds>;
717+
defvar s = !cond(!eq(prefix, NoPre): "r", !eq(prefix, CBPre): "g");
718+
defvar rc8 = !cond(!eq(prefix, NoPre): R8, !eq(prefix, CBPre): G8);
719+
def 8#s : I <Pre<Idx0Pre, prefix>, opcode, mnemonic, "\t$dst", "$imp = $dst",
720+
(outs rc8:$dst), (ins rc8:$imp),
721+
[(set rc8:$dst, F,
722+
(!cast<SDNode>(!strconcat("Z80", mnemonic, "_flag"))
723+
rc8:$imp))]>,
724+
Requires<Preds>;
724725
let mayLoad = true, mayStore = true in {
725-
def 8p : I <Pre<Idx0Pre, prefix>, opcode, mnemonic, "\t$adr", "",
726-
(outs), (ins aptr:$adr),
727-
[(store (!cast<SDNode>(!strconcat("Z80", mnemonic, "_flag"))
728-
(i8 (load iPTR:$adr))), iPTR:$adr),
729-
(implicit F)]>,
730-
Requires<Preds>;
731-
def 8o : Io<Pre<Idx0Pre, prefix>, opcode, mnemonic, "\t$adr", "",
732-
(outs), (ins off:$adr),
733-
[(store (!cast<SDNode>(!strconcat("Z80", mnemonic, "_flag"))
734-
(i8 (load offpat:$adr))), offpat:$adr),
735-
(implicit F)]>,
736-
Requires<Preds>;
726+
def 8p : I <Pre<Idx0Pre, prefix>, opcode, mnemonic, "\t$adr", "",
727+
(outs), (ins aptr:$adr),
728+
[(store (!cast<SDNode>(!strconcat("Z80", mnemonic, "_flag"))
729+
(i8 (load iPTR:$adr))), iPTR:$adr),
730+
(implicit F)]>,
731+
Requires<Preds>;
732+
def 8o : Io<Pre<Idx0Pre, prefix>, opcode, mnemonic, "\t$adr", "",
733+
(outs), (ins off:$adr),
734+
[(store (!cast<SDNode>(!strconcat("Z80", mnemonic, "_flag"))
735+
(i8 (load offpat:$adr))), offpat:$adr),
736+
(implicit F)]>,
737+
Requires<Preds>;
737738
if !eq(prefix, CBPre) then
738-
def 8go : Io<Pre<Idx1Pre, prefix>, opcode, mnemonic, "\t$adr, $dst", "",
739-
(outs rc8:$dst), (ins off:$adr)>,
740-
Requires<!listconcat(Preds, [HaveUndocOps])>;
739+
def 8#s#o : Io<Pre<Idx1Pre, prefix>, opcode, mnemonic, "\t$adr, $dst", "",
740+
(outs rc8:$dst), (ins off:$adr)>,
741+
Requires<!listconcat(Preds, [HaveUndocOps])>;
741742
}
742743
}
743744
let Defs = [F], Uses = [F] in
744745
multiclass UnOp8RFF<OtherPrefix prefix, bits<8> opcode, string mnemonic,
745746
list<Predicate> Preds = []> {
746-
defvar rc8 = !if(!eq(prefix, CBPre), G8, R8);
747-
def 8r : I <Pre<Idx0Pre, prefix>, opcode, mnemonic, "\t$dst", "$imp = $dst",
748-
(outs rc8:$dst), (ins rc8:$imp),
749-
[(set rc8:$dst, F,
750-
(!cast<SDNode>(!strconcat("Z80", mnemonic, "_flag"))
751-
rc8:$imp, F))]>,
752-
Requires<Preds>;
747+
defvar s = !cond(!eq(prefix, NoPre): "r", !eq(prefix, CBPre): "g");
748+
defvar rc8 = !cond(!eq(prefix, NoPre): R8, !eq(prefix, CBPre): G8);
749+
def 8#s : I <Pre<Idx0Pre, prefix>, opcode, mnemonic, "\t$dst", "$imp = $dst",
750+
(outs rc8:$dst), (ins rc8:$imp),
751+
[(set rc8:$dst, F,
752+
(!cast<SDNode>(!strconcat("Z80", mnemonic, "_flag"))
753+
rc8:$imp, F))]>,
754+
Requires<Preds>;
753755
let mayLoad = true, mayStore = true in {
754-
def 8p : I <Pre<Idx0Pre, prefix>, opcode, mnemonic, "\t$adr", "",
755-
(outs), (ins aptr:$adr),
756-
[(store (!cast<SDNode>(!strconcat("Z80", mnemonic, "_flag"))
757-
(i8 (load iPTR:$adr)), F), iPTR:$adr),
758-
(implicit F)]>,
759-
Requires<Preds>;
760-
def 8o : Io<Pre<Idx0Pre, prefix>, opcode, mnemonic, "\t$adr", "",
761-
(outs), (ins off:$adr),
762-
[(store (!cast<SDNode>(!strconcat("Z80", mnemonic, "_flag"))
763-
(i8 (load offpat:$adr)), F), offpat:$adr),
764-
(implicit F)]>,
765-
Requires<Preds>;
756+
def 8p : I <Pre<Idx0Pre, prefix>, opcode, mnemonic, "\t$adr", "",
757+
(outs), (ins aptr:$adr),
758+
[(store (!cast<SDNode>(!strconcat("Z80", mnemonic, "_flag"))
759+
(i8 (load iPTR:$adr)), F), iPTR:$adr),
760+
(implicit F)]>,
761+
Requires<Preds>;
762+
def 8o : Io<Pre<Idx0Pre, prefix>, opcode, mnemonic, "\t$adr", "",
763+
(outs), (ins off:$adr),
764+
[(store (!cast<SDNode>(!strconcat("Z80", mnemonic, "_flag"))
765+
(i8 (load offpat:$adr)), F), offpat:$adr),
766+
(implicit F)]>,
767+
Requires<Preds>;
766768
if !eq(prefix, CBPre) then
767-
def 8go : Io<Pre<Idx1Pre, prefix>, opcode, mnemonic, "\t$adr, $dst", "",
768-
(outs rc8:$dst), (ins off:$adr)>,
769-
Requires<!listconcat(Preds, [HaveUndocOps])>;
769+
def 8#s#o : Io<Pre<Idx1Pre, prefix>, opcode, mnemonic, "\t$adr, $dst", "",
770+
(outs rc8:$dst), (ins off:$adr)>,
771+
Requires<!listconcat(Preds, [HaveUndocOps])>;
770772
}
771773
}
772774
multiclass BinOp8RF<bits<3> opcode, string mnemonic, bit compare = false> {
@@ -839,12 +841,14 @@ multiclass BinOp8RFF<bits<3> opcode, string mnemonic, SDNode node, bit compare =
839841
}
840842
multiclass BinOp8F<Prefix prefix, bits<3> opcode, string mnemonic,
841843
bit compare = false> {
844+
defvar s = !cond(!eq(prefix, Idx0Pre): "r", !eq(prefix, EDPre): "g");
845+
defvar rc8 = !cond(!eq(prefix, Idx0Pre): R8, !eq(prefix, EDPre): G8);
842846
let isCompare = compare, Defs = [F], Uses = [A] in {
843-
def 8ar : I <prefix, {0b10, opcode, 0b000}, mnemonic, "\ta, $src", "",
844-
(outs), (ins R8:$src),
847+
def 8a#s : I <prefix, {0b10, opcode, 0b000}, mnemonic, "\ta, $src", "",
848+
(outs), (ins rc8:$src),
845849
[(set F,
846850
(!cast<SDNode>(!strconcat("Z80", mnemonic, "_flag"))
847-
A, R8:$src))]>;
851+
A, rc8:$src))]>;
848852
def 8ai : Ii<prefix, {0b11, opcode, 0b110}, mnemonic, "\ta, $src", "",
849853
(outs), (ins i8imm:$src),
850854
[(set F,
@@ -940,13 +944,13 @@ defm TST : BinOp8F < EDPre, 4, "tst", true>, Requires<[HaveZ180Ops]>;
940944
def : MnemonicAlias<"sll", "sli">, Requires<[HaveSliOp]>;
941945
def : MnemonicAlias<"sl1", "sli">, Requires<[HaveSliOp]>;
942946

943-
def : Pat<(fshl G8:$reg, G8:$reg, (i8 1)), (RLC8r G8:$reg)>;
944-
def : Pat<(fshl G8:$reg, G8:$reg, (i8 7)), (RRC8r G8:$reg)>;
945-
def : Pat<(shl G8:$reg, (i8 1)), (SLA8r G8:$reg)>;
946-
def : Pat<(sra G8:$reg, (i8 1)), (SRA8r G8:$reg)>;
947-
def : Pat<(or (shl G8:$reg, (i8 1)), (i8 1)), (SLI8r G8:$reg)>,
947+
def : Pat<(fshl G8:$reg, G8:$reg, (i8 1)), (RLC8g G8:$reg)>;
948+
def : Pat<(fshl G8:$reg, G8:$reg, (i8 7)), (RRC8g G8:$reg)>;
949+
def : Pat<(shl G8:$reg, (i8 1)), (SLA8g G8:$reg)>;
950+
def : Pat<(sra G8:$reg, (i8 1)), (SRA8g G8:$reg)>;
951+
def : Pat<(or (shl G8:$reg, (i8 1)), (i8 1)), (SLI8g G8:$reg)>,
948952
Requires<[HaveSliOp]>;
949-
def : Pat<(srl G8:$reg, (i8 1)), (SRL8r G8:$reg)>;
953+
def : Pat<(srl G8:$reg, (i8 1)), (SRL8g G8:$reg)>;
950954
def : Pat<(add R8:$reg, (i8 1)), (INC8r R8:$reg)>;
951955
def : Pat<(add R8:$reg, (i8 -1)), (DEC8r R8:$reg)>;
952956

‎llvm/lib/Target/Z80/Z80MachineLateOptimization.cpp

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -425,18 +425,18 @@ bool Z80MachineLateOptimization::runOnMachineFunction(MachineFunction &MF) {
425425
break;
426426
Val = {KnownFlagsVal, KnownFlagsMask, Reg, *TRI};
427427
break;
428-
case Z80::RLC8r:
429-
case Z80::RRC8r:
430-
case Z80::RL8r:
431-
case Z80::RR8r:
428+
case Z80::RLC8g:
429+
case Z80::RRC8g:
430+
case Z80:: RL8g:
431+
case Z80:: RR8g:
432432
Reg = MIB->getOperand(0).getReg();
433433
if (Reg != Z80::A || !LiveUnits.available(Z80::F))
434434
break;
435435
switch (Opc) {
436-
case Z80::RLC8r: Opc = Z80::RLCA; break;
437-
case Z80::RRC8r: Opc = Z80::RRCA; break;
438-
case Z80::RL8r: Opc = Z80::RLA; break;
439-
case Z80::RR8r: Opc = Z80::RRA; break;
436+
case Z80::RLC8g: Opc = Z80::RLCA; break;
437+
case Z80::RRC8g: Opc = Z80::RRCA; break;
438+
case Z80:: RL8g: Opc = Z80:: RLA; break;
439+
case Z80:: RR8g: Opc = Z80:: RRA; break;
440440
}
441441
LLVM_DEBUG(dbgs() << "Replacing: "; MIB->dump();
442442
dbgs() << " With: ");

‎llvm/lib/Target/Z80/Z80PostSelectCombiner.cpp

Lines changed: 27 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -218,13 +218,13 @@ bool Z80PostSelectCombiner::runOnMachineFunction(MachineFunction &MF) {
218218
case Z80::OR8ai:
219219
SZFlagLoc.setReg(Z80::A);
220220
break;
221-
case Z80::RLC8r:
222-
case Z80::RRC8r:
223-
case Z80::RL8r:
224-
case Z80::RR8r:
225-
case Z80::SLA8r:
226-
case Z80::SRA8r:
227-
case Z80::SRL8r:
221+
case Z80::RLC8g:
222+
case Z80::RRC8g:
223+
case Z80:: RL8g:
224+
case Z80:: RR8g:
225+
case Z80::SLA8g:
226+
case Z80::SRA8g:
227+
case Z80::SRL8g:
228228
case Z80::INC8r:
229229
case Z80::DEC8r:
230230
SZFlagLoc.setReg(MI, 0);
@@ -235,16 +235,16 @@ bool Z80PostSelectCombiner::runOnMachineFunction(MachineFunction &MF) {
235235
case Z80::SBC8ap:
236236
case Z80::AND8ap:
237237
case Z80::XOR8ap:
238-
case Z80::OR8ap:
239-
case Z80::RLC8p:
240-
case Z80::RRC8p:
241-
case Z80::RL8p:
242-
case Z80::RR8p:
243-
case Z80::SLA8p:
244-
case Z80::SRA8p:
245-
case Z80::SRL8p:
246-
case Z80::INC8p:
247-
case Z80::DEC8p:
238+
case Z80:: OR8ap:
239+
case Z80:: RLC8p:
240+
case Z80:: RRC8p:
241+
case Z80:: RL8p:
242+
case Z80:: RR8p:
243+
case Z80:: SLA8p:
244+
case Z80:: SRA8p:
245+
case Z80:: SRL8p:
246+
case Z80:: INC8p:
247+
case Z80:: DEC8p:
248248
SZFlagLoc.setPtr(MI, 0);
249249
break;
250250
case Z80::ADD8ao:
@@ -253,16 +253,16 @@ bool Z80PostSelectCombiner::runOnMachineFunction(MachineFunction &MF) {
253253
case Z80::SBC8ao:
254254
case Z80::AND8ao:
255255
case Z80::XOR8ao:
256-
case Z80::OR8ao:
257-
case Z80::RLC8o:
258-
case Z80::RRC8o:
259-
case Z80::RL8o:
260-
case Z80::RR8o:
261-
case Z80::SLA8o:
262-
case Z80::SRA8o:
263-
case Z80::SRL8o:
264-
case Z80::INC8o:
265-
case Z80::DEC8o:
256+
case Z80:: OR8ao:
257+
case Z80:: RLC8o:
258+
case Z80:: RRC8o:
259+
case Z80:: RL8o:
260+
case Z80:: RR8o:
261+
case Z80:: SLA8o:
262+
case Z80:: SRA8o:
263+
case Z80:: SRL8o:
264+
case Z80:: INC8o:
265+
case Z80:: DEC8o:
266266
SZFlagLoc.setOff(MI, 0);
267267
break;
268268
default:

0 commit comments

Comments
 (0)