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Fix pseudo-instruction name case.
1 parent 150e666 commit 605dcac

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7 files changed

+70
-137
lines changed

7 files changed

+70
-137
lines changed

‎llvm/lib/Target/Z80/GISel/Z80InstructionSelector.cpp

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -1200,13 +1200,13 @@ Z80InstructionSelector::foldCompare(MachineInstr &I, MachineIRBuilder &MIB,
12001200
Reg = Z80::A;
12011201
break;
12021202
case 16:
1203-
Opc = Z80::SUB16ao;
1203+
Opc = Z80::Sub16ao;
12041204
LDIOpc = Z80::LD16ri;
12051205
AddOpc = Z80::ADD16ao;
12061206
Reg = Z80::HL;
12071207
break;
12081208
case 24:
1209-
Opc = Z80::SUB24ao;
1209+
Opc = Z80::Sub24ao;
12101210
LDIOpc = Z80::LD24ri;
12111211
AddOpc = Z80::ADD24ao;
12121212
Reg = Z80::UHL;
@@ -1290,7 +1290,7 @@ Z80InstructionSelector::foldCompare(MachineInstr &I, MachineIRBuilder &MIB,
12901290
Ops = {Reg};
12911291
}
12921292
} else {
1293-
Opc = OpSize == 24 ? Z80::CP24a0 : Z80::CP16a0;
1293+
Opc = OpSize == 24 ? Z80::Cmp24a0 : Z80::Cmp16a0;
12941294
Ops.clear();
12951295
}
12961296
} else if (OpSize == 8) {

‎llvm/lib/Target/Z80/GISel/Z80LegalizerInfo.cpp

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -933,7 +933,7 @@ LegalizerHelper::LegalizeResult Z80LegalizerInfo::legalizeMemIntrinsic(
933933
}
934934
if (Opc == TargetOpcode::G_MEMMOVE && !ConstAddr) {
935935
MIRBuilder.buildCopy(HL, SrcReg);
936-
MIRBuilder.buildInstr(Is24Bit ? Z80::CP24ao : Z80::CP16ao, {},
936+
MIRBuilder.buildInstr(Is24Bit ? Z80::Cmp24ao : Z80::Cmp16ao, {},
937937
{DstReg});
938938
MIRBuilder
939939
.buildInstr(Is24Bit ? Z80::LDR24 : Z80::LDR16, {},

‎llvm/lib/Target/Z80/Z80ISelLowering.cpp

Lines changed: 0 additions & 64 deletions
Original file line numberDiff line numberDiff line change
@@ -299,18 +299,6 @@ Z80TargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
299299
MachineBasicBlock *BB) const {
300300
switch (MI.getOpcode()) {
301301
default: llvm_unreachable("Unexpected instr type to insert");
302-
/*case Z80::Sub016:
303-
case Z80::Sub024:
304-
return EmitLoweredSub0(MI, BB);
305-
case Z80::Sub16:
306-
case Z80::Sub24:
307-
return EmitLoweredSub(MI, BB);
308-
case Z80::Cp16a0:
309-
case Z80::Cp24a0:
310-
return EmitLoweredCmp0(MI, BB);
311-
case Z80::Cp16ao:
312-
case Z80::Cp24ao:
313-
return EmitLoweredCmp(MI, BB);*/
314302
case Z80::SetCC:
315303
case Z80::Select8:
316304
case Z80::Select16:
@@ -352,58 +340,6 @@ void Z80TargetLowering::AdjustAdjCallStack(MachineInstr &MI) const {
352340
LLVM_DEBUG(MI.dump());
353341
}
354342

355-
MachineBasicBlock *
356-
Z80TargetLowering::EmitLoweredSub(MachineInstr &MI,
357-
MachineBasicBlock *BB) const {
358-
bool Is24Bit = MI.getOpcode() == Z80::SUB24ao;
359-
assert((Is24Bit || MI.getOpcode() == Z80::SUB16ao) && "Unexpected opcode");
360-
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
361-
DebugLoc DL = MI.getDebugLoc();
362-
LLVM_DEBUG(BB->dump());
363-
BuildMI(*BB, MI, DL, TII->get(Z80::RCF));
364-
BuildMI(*BB, MI, DL, TII->get(Is24Bit ? Z80::SBC24ao : Z80::SBC16ao))
365-
.addReg(MI.getOperand(0).getReg());
366-
MI.eraseFromParent();
367-
LLVM_DEBUG(BB->dump());
368-
return BB;
369-
}
370-
371-
MachineBasicBlock *
372-
Z80TargetLowering::EmitLoweredCmp(MachineInstr &MI,
373-
MachineBasicBlock *BB) const {
374-
bool Is24Bit = MI.getOpcode() == Z80::CP24ao;
375-
assert((Is24Bit || MI.getOpcode() == Z80::CP16ao) && "Unexpected opcode");
376-
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
377-
DebugLoc DL = MI.getDebugLoc();
378-
BuildMI(*BB, MI, DL, TII->get(Z80::RCF));
379-
BuildMI(*BB, MI, DL, TII->get(Is24Bit ? Z80::SBC24ao : Z80::SBC16ao))
380-
.addReg(MI.getOperand(0).getReg());
381-
BuildMI(*BB, MI, DL, TII->get(Is24Bit ? Z80::ADD24ao : Z80::ADD16ao),
382-
Is24Bit ? Z80::UHL : Z80::HL).addReg(Is24Bit ? Z80::UHL : Z80::HL)
383-
.addReg(MI.getOperand(0).getReg());
384-
MI.eraseFromParent();
385-
LLVM_DEBUG(BB->dump());
386-
return BB;
387-
}
388-
389-
MachineBasicBlock *
390-
Z80TargetLowering::EmitLoweredCmp0(MachineInstr &MI,
391-
MachineBasicBlock *BB) const {
392-
bool Is24Bit = MI.getOpcode() == Z80::CP24a0;
393-
assert((Is24Bit || MI.getOpcode() == Z80::CP16a0) && "Unexpected opcode");
394-
const TargetInstrInfo *TII = Subtarget.getInstrInfo();
395-
DebugLoc DL = MI.getDebugLoc();
396-
BuildMI(*BB, MI, DL, TII->get(Is24Bit ? Z80::ADD24ao : Z80::ADD16ao),
397-
Is24Bit ? Z80::UHL : Z80::HL).addReg(Is24Bit ? Z80::UHL : Z80::HL)
398-
.addReg(MI.getOperand(0).getReg());
399-
BuildMI(*BB, MI, DL, TII->get(Z80::RCF));
400-
BuildMI(*BB, MI, DL, TII->get(Is24Bit ? Z80::SBC24ao : Z80::SBC16ao))
401-
.addReg(MI.getOperand(0).getReg());
402-
MI.eraseFromParent();
403-
LLVM_DEBUG(BB->dump());
404-
return BB;
405-
}
406-
407343
MachineBasicBlock *
408344
Z80TargetLowering::EmitLoweredSelect(MachineInstr &MI,
409345
MachineBasicBlock *BB) const {

‎llvm/lib/Target/Z80/Z80ISelLowering.h

Lines changed: 0 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -108,14 +108,6 @@ class Z80TargetLowering final : public TargetLowering {
108108
SDNode *Node) const override;
109109

110110
void AdjustAdjCallStack(MachineInstr &MI) const;
111-
MachineBasicBlock *EmitLoweredSub0(MachineInstr &MI,
112-
MachineBasicBlock *BB) const;
113-
MachineBasicBlock *EmitLoweredSub(MachineInstr &MI,
114-
MachineBasicBlock *BB) const;
115-
MachineBasicBlock *EmitLoweredCmp0(MachineInstr &MI,
116-
MachineBasicBlock *BB) const;
117-
MachineBasicBlock *EmitLoweredCmp(MachineInstr &MI,
118-
MachineBasicBlock *BB) const;
119111
MachineBasicBlock *EmitLoweredSelect(MachineInstr &MI,
120112
MachineBasicBlock *BB) const;
121113
MachineBasicBlock *EmitLoweredSExt(MachineInstr &MI,

‎llvm/lib/Target/Z80/Z80InstrInfo.cpp

Lines changed: 40 additions & 35 deletions
Original file line numberDiff line numberDiff line change
@@ -1203,34 +1203,34 @@ bool Z80InstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
12031203
->ChangeToImmediate(Opc == Z80::LD24r0 ? 0 : -1);
12041204
}
12051205
break;
1206-
case Z80::CP16ao:
1207-
case Z80::CP24ao: {
1208-
MCRegister Reg = Opc == Z80::CP24ao ? Z80::UHL : Z80::HL;
1206+
case Z80::Cmp16ao:
1207+
case Z80::Cmp24ao: {
1208+
MCRegister Reg = Opc == Z80::Cmp24ao ? Z80::UHL : Z80::HL;
12091209
if (MBB.computeRegisterLiveness(&TRI, Reg, Next) !=
12101210
MachineBasicBlock::LQR_Dead) {
1211-
BuildMI(MBB, Next, DL, get(Opc == Z80::CP24ao ? Z80::ADD24ao
1212-
: Z80::ADD16ao), Reg)
1213-
.addReg(Reg).add(MI.getOperand(0));
1211+
BuildMI(MBB, Next, DL,
1212+
get(Opc == Z80::Cmp24ao ? Z80::ADD24ao : Z80::ADD16ao), Reg)
1213+
.addReg(Reg).add(MI.getOperand(0));
12141214
MI.getOperand(0).setIsKill(false);
12151215
}
12161216
MIB.addReg(Reg, RegState::ImplicitDefine);
12171217
LLVM_FALLTHROUGH;
12181218
}
1219-
case Z80::SUB16ao:
1220-
case Z80::SUB24ao:
1219+
case Z80::Sub16ao:
1220+
case Z80::Sub24ao:
12211221
expandPostRAPseudo(*BuildMI(MBB, MI, DL, get(Z80::RCF)));
1222-
MI.setDesc(get(Opc == Z80::CP24ao || Opc == Z80::SUB24ao ? Z80::SBC24ao
1223-
: Z80::SBC16ao));
1222+
MI.setDesc(get(Opc == Z80::Cmp24ao || Opc == Z80::Sub24ao ? Z80::SBC24ao
1223+
: Z80::SBC16ao));
12241224
MIB.addReg(Z80::F, RegState::Implicit);
12251225
break;
1226-
case Z80::CP16a0:
1227-
case Z80::CP24a0: {
1228-
MCRegister Reg = Opc == Z80::CP24a0 ? Z80::UHL : Z80::HL;
1229-
MCRegister UndefReg = Opc == Z80::CP24a0 ? Z80::UBC : Z80::BC;
1230-
BuildMI(MBB, MI, DL, get(Opc == Z80::CP24a0 ? Z80::ADD24ao : Z80::ADD16ao),
1226+
case Z80::Cmp16a0:
1227+
case Z80::Cmp24a0: {
1228+
MCRegister Reg = Opc == Z80::Cmp24a0 ? Z80::UHL : Z80::HL;
1229+
MCRegister UndefReg = Opc == Z80::Cmp24a0 ? Z80::UBC : Z80::BC;
1230+
BuildMI(MBB, MI, DL, get(Opc == Z80::Cmp24a0 ? Z80::ADD24ao : Z80::ADD16ao),
12311231
Reg).addReg(Reg).addReg(UndefReg, RegState::Undef);
12321232
expandPostRAPseudo(*BuildMI(MBB, MI, DL, get(Z80::RCF)));
1233-
MI.setDesc(get(Opc == Z80::CP24a0 ? Z80::SBC24ao : Z80::SBC16ao));
1233+
MI.setDesc(get(Opc == Z80::Cmp24a0 ? Z80::SBC24ao : Z80::SBC16ao));
12341234
MIB.addReg(UndefReg, RegState::Undef).addReg(Reg, RegState::ImplicitDefine)
12351235
.addReg(Z80::F, RegState::Implicit);
12361236
break;
@@ -1581,25 +1581,30 @@ inline static bool isRedundantFlagInstr(MachineInstr &FI, Register SrcReg,
15811581
inline static bool isSZSettingInstr(MachineInstr &MI) {
15821582
switch (MI.getOpcode()) {
15831583
default: return false;
1584-
case Z80::INC8r: case Z80::INC8p: case Z80::INC8o:
1585-
case Z80::DEC8r: case Z80::DEC8p: case Z80::DEC8o:
1586-
case Z80::ADD8ar: case Z80::ADD8ai: case Z80::ADD8ap: case Z80::ADD8ao:
1587-
case Z80::ADC8ar: case Z80::ADC8ai: case Z80::ADC8ap: case Z80::ADC8ao:
1588-
case Z80::SUB8ar: case Z80::SUB8ai: case Z80::SUB8ap: case Z80::SUB8ao:
1589-
case Z80::SBC8ar: case Z80::SBC8ai: case Z80::SBC8ap: case Z80::SBC8ao:
1590-
case Z80::AND8ar: case Z80::AND8ai: case Z80::AND8ap: case Z80::AND8ao:
1591-
case Z80::XOR8ar: case Z80::XOR8ai: case Z80::XOR8ap: case Z80::XOR8ao:
1592-
case Z80:: OR8ar: case Z80:: OR8ai: case Z80:: OR8ap: case Z80:: OR8ao:
1593-
case Z80::TST8ag: case Z80::TST8ai: case Z80::TST8ap:
1594-
case Z80::SBC16ao:case Z80::NEG: case Z80::ADC16ao:
1595-
case Z80::SUB16ao:case Z80::SUB24ao:
1596-
case Z80::RLC8g: case Z80::RLC8p: case Z80::RLC8o:
1597-
case Z80::RRC8g: case Z80::RRC8p: case Z80::RRC8o:
1598-
case Z80:: RL8g: case Z80:: RL8p: case Z80:: RL8o:
1599-
case Z80:: RR8g: case Z80:: RR8p: case Z80:: RR8o:
1600-
case Z80::SLA8g: case Z80::SLA8p: case Z80::SLA8o:
1601-
case Z80::SRA8g: case Z80::SRA8p: case Z80::SRA8o:
1602-
case Z80::SRL8g: case Z80::SRL8p: case Z80::SRL8o:
1584+
case Z80::INC8r: case Z80::INC8p: case Z80::INC8o:
1585+
case Z80::DEC8r: case Z80::DEC8p: case Z80::DEC8o:
1586+
case Z80::ADD8ar: case Z80::ADD8ai: case Z80::ADD8ap: case Z80::ADD8ao:
1587+
case Z80::ADC8ar: case Z80::ADC8ai: case Z80::ADC8ap: case Z80::ADC8ao:
1588+
case Z80::SUB8ar: case Z80::SUB8ai: case Z80::SUB8ap: case Z80::SUB8ao:
1589+
case Z80::SBC8ar: case Z80::SBC8ai: case Z80::SBC8ap: case Z80::SBC8ao:
1590+
case Z80::AND8ar: case Z80::AND8ai: case Z80::AND8ap: case Z80::AND8ao:
1591+
case Z80::XOR8ar: case Z80::XOR8ai: case Z80::XOR8ap: case Z80::XOR8ao:
1592+
case Z80:: OR8ar: case Z80:: OR8ai: case Z80:: OR8ap: case Z80:: OR8ao:
1593+
case Z80::TST8ag: case Z80::TST8ai: case Z80::TST8ap:
1594+
case Z80::NEG: case Z80::Sub16ao: case Z80::Sub24ao:
1595+
case Z80::ADD16aa: case Z80::ADD16ao: case Z80::ADD16as:
1596+
case Z80::SBC16aa: case Z80::SBC16ao: case Z80::SBC16as:
1597+
case Z80::ADC16aa: case Z80::ADC16ao: case Z80::ADC16as:
1598+
case Z80::ADD24aa: case Z80::ADD24ao: case Z80::ADD24as:
1599+
case Z80::SBC24aa: case Z80::SBC24ao: case Z80::SBC24as:
1600+
case Z80::ADC24aa: case Z80::ADC24ao: case Z80::ADC24as:
1601+
case Z80::RLC8g: case Z80::RLC8p: case Z80::RLC8o:
1602+
case Z80::RRC8g: case Z80::RRC8p: case Z80::RRC8o:
1603+
case Z80:: RL8g: case Z80:: RL8p: case Z80:: RL8o:
1604+
case Z80:: RR8g: case Z80:: RR8p: case Z80:: RR8o:
1605+
case Z80::SLA8g: case Z80::SLA8p: case Z80::SLA8o:
1606+
case Z80::SRA8g: case Z80::SRA8p: case Z80::SRA8o:
1607+
case Z80::SRL8g: case Z80::SRL8p: case Z80::SRL8o:
16031608
return true;
16041609
}
16051610
}

‎llvm/lib/Target/Z80/Z80InstrInfo.td

Lines changed: 14 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -1066,32 +1066,32 @@ def : Pat<(sube UHL, O24:$src), (SBC24ao O24:$src)>;
10661066
def : Pat<(adde UHL, O24:$src), (ADC24ao O24:$src)>;
10671067

10681068
let Defs = [HL, F], Uses = [HL] in {
1069-
def SUB16ao : P<(outs), (ins O16:$src),
1069+
def Sub16ao : P<(outs), (ins O16:$src),
10701070
[(set HL, F, (Z80sub_flag HL, O16:$src))]>;
10711071
}
10721072
let Defs = [UHL, F], Uses = [UHL] in {
1073-
def SUB24ao : P<(outs), (ins O24:$src),
1073+
def Sub24ao : P<(outs), (ins O24:$src),
10741074
[(set UHL, F, (Z80sub_flag UHL, O24:$src))]>,
10751075
Requires<[HaveEZ80Ops]>;
10761076
}
10771077
let Defs = [F] in {
10781078
let Uses = [HL] in {
1079-
def CP16a0 : P<(outs), (ins), [(set F, (Z80cp_flag HL, 0))]>;
1080-
def CP16ao : P<(outs), (ins O16:$src),
1081-
[(set F, (Z80cp_flag HL, O16:$src))]>;
1079+
def Cmp16a0 : P<(outs), (ins), [(set F, (Z80cp_flag HL, 0))]>;
1080+
def Cmp16ao : P<(outs), (ins O16:$src),
1081+
[(set F, (Z80cp_flag HL, O16:$src))]>;
10821082
}
10831083
let Uses = [UHL] in {
1084-
def CP24a0 : P<(outs), (ins), [(set F, (Z80cp_flag UHL, 0))]>,
1085-
Requires<[HaveEZ80Ops]>;
1086-
def CP24ao : P<(outs), (ins O24:$src),
1087-
[(set F, (Z80cp_flag UHL, O24:$src))]>,
1088-
Requires<[HaveEZ80Ops]>;
1084+
def Cmp24a0 : P<(outs), (ins), [(set F, (Z80cp_flag UHL, 0))]>,
1085+
Requires<[HaveEZ80Ops]>;
1086+
def Cmp24ao : P<(outs), (ins O24:$src),
1087+
[(set F, (Z80cp_flag UHL, O24:$src))]>,
1088+
Requires<[HaveEZ80Ops]>;
10891089
}
10901090
}
1091-
def : Pat<(sub HL, O16:$src), (SUB16ao O16:$src)>;
1092-
def : Pat<(sub UHL, O24:$src), (SUB24ao O24:$src)>;
1093-
def : Pat<(subc HL, O16:$src), (SUB16ao O16:$src)>;
1094-
def : Pat<(subc UHL, O24:$src), (SUB24ao O24:$src)>;
1091+
def : Pat<(sub HL, O16:$src), (Sub16ao O16:$src)>;
1092+
def : Pat<(sub UHL, O24:$src), (Sub24ao O24:$src)>;
1093+
def : Pat<(subc HL, O16:$src), (Sub16ao O16:$src)>;
1094+
def : Pat<(subc UHL, O24:$src), (Sub24ao O24:$src)>;
10951095

10961096
def LEA16ro : I16o<EDPre, 0x02, "lea", "\t$dst, $src", "",
10971097
(outs R16:$dst), (ins off16:$src),

‎llvm/lib/Target/Z80/Z80MachineLateOptimization.cpp

Lines changed: 12 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -362,8 +362,8 @@ Z80MachineLateOptimization::getKnownFlags(const MachineInstr &MI,
362362
isKnownSpecificImm(Opc == Z80::SBC16as ? Z80::SPS : Z80::SPL, 0)))
363363
return {SubtractFlag, HalfCarryFlag | ParityOverflowFlag | CarryFlag};
364364
return {SubtractFlag};
365-
case Z80::SUB16ao:
366-
case Z80::SUB24ao:
365+
case Z80::Sub16ao:
366+
case Z80::Sub24ao:
367367
return {SubtractFlag};
368368
}
369369
return {};
@@ -507,23 +507,23 @@ bool Z80MachineLateOptimization::runOnMachineFunction(MachineFunction &MF) {
507507
MIB->getOperand(0).setImplicit();
508508
MIB->getOperand(1).setImplicit();
509509
break;
510-
case Z80::SUB16ao:
511-
case Z80::SUB24ao:
512-
case Z80::CP16ao:
513-
case Z80::CP24ao: {
510+
case Z80::Sub16ao:
511+
case Z80::Sub24ao:
512+
case Z80::Cmp16ao:
513+
case Z80::Cmp24ao: {
514514
if (!(~KnownFlagsVal & KnownFlagsMask & CarryFlag))
515515
break;
516516
MCRegister DstReg;
517517
unsigned SubOpc, AddOpc;
518518
switch (Opc) {
519-
case Z80::SUB16ao:
520-
case Z80::CP16ao:
519+
case Z80::Sub16ao:
520+
case Z80::Cmp16ao:
521521
DstReg = Z80::HL;
522522
SubOpc = Z80::SBC16ao;
523523
AddOpc = Z80::ADD16ao;
524524
break;
525-
case Z80::SUB24ao:
526-
case Z80::CP24ao:
525+
case Z80::Sub24ao:
526+
case Z80::Cmp24ao:
527527
DstReg = Z80::UHL;
528528
SubOpc = Z80::SBC24ao;
529529
AddOpc = Z80::ADD24ao;
@@ -534,8 +534,8 @@ bool Z80MachineLateOptimization::runOnMachineFunction(MachineFunction &MF) {
534534
MIB->setDesc(TII.get(SubOpc));
535535
MIB.addReg(Z80::F, RegState::Implicit | getKillRegState(reuse(Z80::F)));
536536
switch (Opc) {
537-
case Z80::CP16ao:
538-
case Z80::CP24ao:
537+
case Z80::Cmp16ao:
538+
case Z80::Cmp24ao:
539539
MIB.addReg(DstReg, RegState::ImplicitDefine);
540540
if (LiveUnits.available(DstReg))
541541
break;

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