arm: dts: fix adi,axi-pwmgen clocks

dlech · dlech · commit f43c9f5efeb7 · 2025-06-25T09:27:08.000-06:00
After backporting the dt-bindings fix from upstream, update the existing
.dts files that use adi,axi-pwmgen-2.00.a to use the corrected clocks
binding.

In the HDL, ASYNC_CLK_EN=1 by default, so most projects have a separate
external clock. The only exceptions are ad7606x, ad7616 and dc2677a,
which have ASYNC_CLK_EN=0 and therefore only one clock.

In arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4134.dts the wrong clock
was specified for the old binding so it will have a behavior change to
use the correct clock for the PWM clock rate now.

In arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ltc2387.dts, we also drop
the 0 in the phandle since #clock-cells = &lt;0&gt;; for &amp;ref_clk.

Signed-off-by: David Lechner &lt;dlechner@baylibre.com&gt;
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10_nano_ad5791.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_de10_nano_ad5791.dts
@@ -45,7 +45,8 @@
 		compatible = "adi,axi-pwmgen-2.00.a";
 		reg = <0x00050000 0x1000>;
 		#pwm-cells = <3>;
-		clocks = <&spi_clk 0>;
+		clocks = <&sys_clk>, <&spi_clk 0>;
+		clock-names = "axi", "ext";
 	};
 
 	tx_dma: dma-controller@30000 {
diff --git a/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sockit_dc2677a.dts b/arch/arm/boot/dts/intel/socfpga/socfpga_cyclone5_sockit_dc2677a.dts
@@ -140,6 +140,7 @@
 					reg = <0x00040000 0x1000>;
 					#pwm-cells = <2>;
 					clocks = <&sys_clk>;
+					clock-names = "axi";
 				};
 
 				gpio: gpio@9000 {
diff --git a/arch/arm/boot/dts/xilinx/zynq-coraz7s-ad7689-ardz.dts b/arch/arm/boot/dts/xilinx/zynq-coraz7s-ad7689-ardz.dts
@@ -32,7 +32,8 @@
 		reg = <0x44b00000 0x1000>;
 		label = "adc_conversion_trigger";
 		#pwm-cells = <2>;
-		clocks = <&spi_clk>;
+		clocks = <&clkc 15>, <&spi_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	spi_engine: spi@44a00000 {
diff --git a/arch/arm/boot/dts/xilinx/zynq-coraz7s-ad7946.dts b/arch/arm/boot/dts/xilinx/zynq-coraz7s-ad7946.dts
@@ -32,7 +32,8 @@
 		reg = <0x44b00000 0x1000>;
 		label = "adc_conversion_trigger";
 		#pwm-cells = <2>;
-		clocks = <&spi_clk>;
+		clocks = <&clkc 15>, <&spi_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	spi_engine: spi@44a00000 {
diff --git a/arch/arm/boot/dts/xilinx/zynq-coraz7s-ad7984.dts b/arch/arm/boot/dts/xilinx/zynq-coraz7s-ad7984.dts
@@ -32,7 +32,8 @@
 		reg = <0x44b00000 0x1000>;
 		label = "adc_conversion_trigger";
 		#pwm-cells = <2>;
-		clocks = <&spi_clk>;
+		clocks = <&clkc 15>, <&spi_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	spi_engine: spi@44a00000 {
diff --git a/arch/arm/boot/dts/xilinx/zynq-coraz7s-adaq4001.dts b/arch/arm/boot/dts/xilinx/zynq-coraz7s-adaq4001.dts
@@ -53,7 +53,8 @@
 		reg = <0x44b00000 0x1000>;
 		label = "adc_conversion_trigger";
 		#pwm-cells = <2>;
-		clocks = <&spi_clk>;
+		clocks = <&clkc 15>, <&spi_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	spi_engine: spi@44a00000 {
diff --git a/arch/arm/boot/dts/xilinx/zynq-coraz7s-adaq4003.dts b/arch/arm/boot/dts/xilinx/zynq-coraz7s-adaq4003.dts
@@ -53,7 +53,8 @@
 		reg = <0x44b00000 0x1000>;
 		label = "adc_conversion_trigger";
 		#pwm-cells = <2>;
-		clocks = <&spi_clk>;
+		clocks = <&clkc 15>, <&spi_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	spi_engine: spi@44a00000 {
diff --git a/arch/arm/boot/dts/xilinx/zynq-coraz7s-pulsar.dtsi b/arch/arm/boot/dts/xilinx/zynq-coraz7s-pulsar.dtsi
@@ -52,7 +52,8 @@
 		reg = <0x44b00000 0x1000>;
 		label = "adc_conversion_trigger";
 		#pwm-cells = <2>;
-		clocks = <&spi_clk>;
+		clocks = <&clkc 15>, <&spi_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	spi_engine: spi@44a00000 {
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4000.dtsi b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4000.dtsi
@@ -56,7 +56,8 @@
 		reg = <0x44b00000 0x1000>;
 		label = "adc_conversion_trigger";
 		#pwm-cells = <2>;
-		clocks = <&spi_clk>;
+		clocks = <&clkc 15>, <&spi_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	spi_engine: spi@0x44a00000 {
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4030-24.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4030-24.dts
@@ -72,8 +72,8 @@
 		reg = <0x44b00000 0x1000>;
 		label = "ad463x_cnv";
 		#pwm-cells = <2>;
-		clocks = <&cnv_ext_clk>;
-
+		clocks = <&clkc 15>, <&cnv_ext_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	axi_spi_engine: spi@44a00000 {
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4032-24.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4032-24.dts
@@ -72,8 +72,8 @@
 		reg = <0x44b00000 0x1000>;
 		label = "ad463x_cnv";
 		#pwm-cells = <2>;
-		clocks = <&cnv_ext_clk>;
-
+		clocks = <&clkc 15>, <&cnv_ext_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	axi_spi_engine: spi@44a00000 {
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4134.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4134.dts
@@ -91,7 +91,8 @@
 		compatible = "adi,axi-pwmgen-2.00.a";
 		reg = <0x44b00000 0x10000>;
 		#pwm-cells = <2>;
-		clocks = <&clkc 15>;
+		clocks = <&clkc 15>, <&spi_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	spi_clk: clock-controller@44b10000 {
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4630-16.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4630-16.dts
@@ -72,8 +72,8 @@
 		reg = <0x44b00000 0x1000>;
 		label = "ad463x_cnv";
 		#pwm-cells = <2>;
-		clocks = <&cnv_ext_clk>;
-
+		clocks = <&clkc 15>, <&cnv_ext_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	axi_spi_engine: spi@44a00000 {
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4630-24.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4630-24.dts
@@ -60,7 +60,8 @@
 		compatible = "adi,axi-pwmgen-2.00.a";
 		reg = <0x44b00000 0x1000>;
 		#pwm-cells = <3>;
-		clocks = <&cnv_ext_clk>;
+		clocks = <&clkc 15>, <&cnv_ext_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	rx_dma: dma-controller@44a30000 {
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4696.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad4696.dts
@@ -70,7 +70,8 @@
 		compatible = "adi,axi-pwmgen-2.00.a";
 		reg = <0x44b00000 0x1000>;
 		#pwm-cells = <3>;
-		clocks = <&spi_clk>;
+		clocks = <&clkc 15>, <&spi_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	spi_clk: clock-controller@44a70000 {
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad7380.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad7380.dts
@@ -60,7 +60,8 @@
 		reg = <0x44b00000 0x1000>;
 		label = "adc_conversion_trigger";
 		#pwm-cells = <3>;
-		clocks = <&spi_clk>;
+		clocks = <&clkc 15>, <&spi_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	spi_clk: clock-controller@44a70000 {
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad7625.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad7625.dts
@@ -81,7 +81,8 @@
 		reg = <0x44a60000 0x1000>;
 		label = "adc_conversion_trigger";
 		#pwm-cells = <3>;
-		clocks = <&ref_clk>;
+		clocks = <&clkc 15>, <&ref_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	iio_backend: backend@44a00000{
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad7944.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad7944.dts
@@ -56,7 +56,8 @@
 		compatible = "adi,axi-pwmgen-2.00.a";
 		reg = <0x44b00000 0x1000>;
 		#pwm-cells = <2>;
-		clocks = <&spi_clk>;
+		clocks = <&clkc 15>, <&spi_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	rx_dma: dma-controller@44a30000 {
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad7960.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad7960.dts
@@ -83,7 +83,8 @@
 		reg = <0x44a60000 0x1000>;
 		label = "adc_conversion_trigger";
 		#pwm-cells = <3>;
-		clocks = <&ref_clk>;
+		clocks = <&clkc 15>, <&ref_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	iio_backend: backend@44a00000{
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad7985.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad7985.dts
@@ -56,7 +56,8 @@
 		compatible = "adi,axi-pwmgen-2.00.a";
 		reg = <0x44b00000 0x1000>;
 		#pwm-cells = <2>;
-		clocks = <&spi_clk>;
+		clocks = <&clkc 15>, <&spi_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	rx_dma: dma-controller@44a30000 {
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad7986.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ad7986.dts
@@ -56,7 +56,8 @@
 		compatible = "adi,axi-pwmgen-2.00.a";
 		reg = <0x44b00000 0x1000>;
 		#pwm-cells = <2>;
-		clocks = <&spi_clk>;
+		clocks = <&clkc 15>, <&spi_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	rx_dma: dma-controller@44a30000 {
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4216.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4216.dts
@@ -88,7 +88,8 @@
 		reg = <0x44b00000 0x1000>;
 		label = "ad463x_cnv";
 		#pwm-cells = <2>;
-		clocks = <&cnv_ext_clk>;
+		clocks = <&clkc 15>, <&cnv_ext_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	axi_spi_engine: spi@44a00000 {
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4220.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4220.dts
@@ -99,7 +99,8 @@
 		reg = <0x44b00000 0x1000>;
 		label = "ad463x_cnv";
 		#pwm-cells = <2>;
-		clocks = <&cnv_ext_clk>;
+		clocks = <&clkc 15>, <&cnv_ext_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	axi_spi_engine: spi@44a00000 {
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4224-24.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4224-24.dts
@@ -99,7 +99,8 @@
 		reg = <0x44b00000 0x1000>;
 		label = "ad463x_cnv";
 		#pwm-cells = <2>;
-		clocks = <&cnv_ext_clk>;
+		clocks = <&clkc 15>, <&cnv_ext_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	axi_spi_engine: spi@44a00000 {
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4224-24_cm0_sdi4_cz2.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4224-24_cm0_sdi4_cz2.dts
@@ -86,8 +86,8 @@
 		reg = <0x44b00000 0x1000>;
 		label = "ad463x_cnv";
 		#pwm-cells = <2>;
-		clocks = <&cnv_ext_clk>;
-
+		clocks = <&clkc 15>, <&cnv_ext_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	i2c@41620000 {
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4380-4.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-adaq4380-4.dts
@@ -53,7 +53,8 @@
 		compatible = "adi,axi-pwmgen-2.00.a";
 		reg = <0x44b00000 0x1000>;
 		#pwm-cells = <3>;
-		clocks = <&spi_clk>;
+		clocks = <&clkc 15>, <&spi_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	spi_clk: clock-controller@44a70000 {
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-cn0577.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-cn0577.dts
@@ -61,7 +61,8 @@
 		reg = <0x44a60000 0x1000>;
 		label = "ltc2387_if";
 		#pwm-cells = <2>;
-		clocks = <&ext_clk>;
+		clocks = <&clkc 15>, <&ext_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	ltc2387@0{
diff --git a/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ltc2387.dts b/arch/arm/boot/dts/xilinx/zynq-zed-adv7511-ltc2387.dts
@@ -48,7 +48,8 @@
 		reg = <0x44a60000 0x1000>;
 		label = "ltc2387_if";
 		#pwm-cells = <2>;
-		clocks = <&ref_clk 0>;
+		clocks = <&clkc 15>, <&ref_clk>;
+		clock-names = "axi", "ext";
 	};
 
 	ltc2387: adc@0{
