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dylanmckaydylanmckay
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Implement the Timer16 trait
1 parent a7e32a3 commit 3803ac8

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6 files changed

+65
-34
lines changed

6 files changed

+65
-34
lines changed

‎build.rs

Lines changed: 37 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -71,7 +71,7 @@ fn generate_cores_mod_rs(mcus: &[Mcu]) -> Result<(), io::Error> {
7171
fn write_core_module(mcu: &Mcu, w: &mut Write) -> Result<(), io::Error> {
7272
writeln!(w, "//! Core for {}.", mcu.device.name)?;
7373
writeln!(w)?;
74-
writeln!(w, "use {{Mask, Bitset, HardwareUsart, Register}};")?;
74+
writeln!(w, "use {{Mask, Bitset, Register}};")?;
7575
writeln!(w, "use modules;")?;
7676
writeln!(w)?;
7777

@@ -221,7 +221,7 @@ mod gen {
221221
writeln!(w, "/// The {} module.", usart.name)?;
222222
writeln!(w, "pub struct {};", usart.name)?;
223223
writeln!(w)?;
224-
writeln!(w, "impl HardwareUsart for {} {{", usart.name)?;
224+
writeln!(w, "impl modules::HardwareUsart for {} {{", usart.name)?;
225225
for register in usart.registers.iter() {
226226
let reg_ty = if register.name.starts_with("UDR") { // the data register.
227227
"DataRegister".to_owned()
@@ -276,6 +276,41 @@ mod gen {
276276
writeln!(w, "}}")?;
277277
}
278278

279+
if let Some(tc) = mcu.module("TC16") { // Timer/Counter, 16-bit.
280+
const TYPE_NAME: &'static str = "Timer16";
281+
282+
let find_reg = |name: &'static str| {
283+
tc.registers().find(|r| r.name.starts_with(name))
284+
.expect(&format!("could not find '{}' register", name))
285+
};
286+
let find_reg_suffix = |name: &'static str, suffix: &'static str| {
287+
tc.registers().find(|r| r.name.starts_with(name) && r.name.ends_with(suffix))
288+
.expect(&format!("could not find '{}' register", name))
289+
};
290+
291+
writeln!(w, "/// 16-bit timer.")?;
292+
writeln!(w, "pub struct {};", TYPE_NAME)?;
293+
writeln!(w)?;
294+
writeln!(w, "impl modules::Timer16 for {} {{", TYPE_NAME)?;
295+
writeln!(w, " type CompareA = {};", find_reg_suffix("OCR", "A").name)?;
296+
writeln!(w, " type CompareB = {};", find_reg_suffix("OCR", "B").name)?;
297+
writeln!(w, " type Counter = {};", find_reg("TCNT").name)?;
298+
writeln!(w, " type ControlA = {};", find_reg_suffix("TCCR", "A").name)?;
299+
writeln!(w, " type ControlB = {};", find_reg_suffix("TCCR", "B").name)?;
300+
writeln!(w, " type ControlC = {};", find_reg_suffix("TCCR", "C").name)?;
301+
writeln!(w, " type InterruptMask = {};", find_reg("TIMSK").name)?;
302+
writeln!(w, " type InterruptFlag = {};", find_reg("TIFR").name)?;
303+
writeln!(w, " const CS0: Mask<u8, Self::ControlB> = Self::ControlB::CS10;")?;
304+
writeln!(w, " const CS1: Mask<u8, Self::ControlB> = Self::ControlB::CS11;")?;
305+
writeln!(w, " const CS2: Mask<u8, Self::ControlB> = Self::ControlB::CS12;")?;
306+
writeln!(w, " const WGM0: Mask<u8, Self::ControlA> = Self::ControlA::WGM10;")?;
307+
writeln!(w, " const WGM1: Mask<u8, Self::ControlA> = Self::ControlA::WGM11;")?;
308+
writeln!(w, " const WGM2: Mask<u8, Self::ControlB> = Self::ControlB::WGM10;")?;
309+
writeln!(w, " const WGM3: Mask<u8, Self::ControlB> = Self::ControlB::WGM11;")?;
310+
writeln!(w, " const OCIEA: Bitset<u8, Self::InterruptMask> = Self::InterruptMask::OCIE1A;")?;
311+
writeln!(w, "}}")?;
312+
}
313+
279314
Ok(())
280315
}
281316

‎src/lib.rs

Lines changed: 0 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -10,7 +10,6 @@
1010

1111
pub use self::register::{Bitset, Mask, Register, RegisterValue};
1212
pub use self::pin::Pin;
13-
pub use self::usart::HardwareUsart;
1413

1514
pub mod prelude;
1615
pub mod serial;
@@ -21,7 +20,6 @@ pub mod config;
2120

2221
mod register;
2322
mod pin;
24-
mod usart;
2523
#[doc(hidden)]
2624
pub mod std_stub;
2725

‎src/modules/mod.rs

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -2,7 +2,9 @@
22
33
pub use self::spi::HardwareSpi;
44
pub use self::timer::{Timer8, Timer8Setup, Timer16, Timer16Setup};
5+
pub use self::usart::HardwareUsart;
56

67
mod spi;
78
mod timer;
9+
mod usart;
810

‎src/modules/timer/timer16.rs

Lines changed: 17 additions & 18 deletions
Original file line numberDiff line numberDiff line change
@@ -48,9 +48,11 @@ pub trait Timer16 {
4848
const WGM0: Mask<u8, Self::ControlA>;
4949
const WGM1: Mask<u8, Self::ControlA>;
5050
const WGM2: Mask<u8, Self::ControlB>;
51-
const WGM3: Mask<u8, Self::ControlB>; // fixme: right reg?
51+
const WGM3: Mask<u8, Self::ControlB>;
5252

5353
const OCIEA: Bitset<u8, Self::InterruptMask>;
54+
55+
fn setup() -> Timer16Setup<T> { Timer16Setup::new() }
5456
}
5557

5658
pub enum ClockSource {
@@ -152,7 +154,7 @@ pub struct Timer16Setup<T: Timer16> {
152154

153155
impl<T: Timer16> Timer16Setup<T> {
154156
#[inline]
155-
pub fn new() -> Self {
157+
fn new() -> Self {
156158
Timer16Setup {
157159
a: Mask::zero(),
158160
b: Mask::zero(),
@@ -190,22 +192,19 @@ impl<T: Timer16> Timer16Setup<T> {
190192

191193
#[inline]
192194
pub fn configure(self) {
193-
unsafe {
194-
T::ControlA::write(self.a);
195-
T::ControlB::write(self.b);
196-
T::ControlC::write(self.c);
197-
198-
// Reset counter to zero
199-
T::Counter::write(0u16);
200-
201-
if let Some(v) = self.output_compare_1 {
202-
// Set the match
203-
T::CompareA::write(v);
204-
205-
// Enable compare interrupt
206-
// FIXME: uncomment
207-
// write_volatile(TIMSK1, OCIE1A);
208-
}
195+
T::ControlA::write(self.a);
196+
T::ControlB::write(self.b);
197+
T::ControlC::write(self.c);
198+
199+
// Reset counter to zero
200+
T::Counter::write(0u16);
201+
202+
if let Some(v) = self.output_compare_1 {
203+
// Set the match
204+
T::CompareA::write(v);
205+
206+
// Enable compare interrupt
207+
T::OCIEA.set_all();
209208
}
210209
}
211210
}

‎src/modules/timer/timer8.rs

Lines changed: 9 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -165,21 +165,18 @@ impl<T: Timer8> Timer8Setup<T> {
165165

166166
#[inline]
167167
pub fn configure(self) {
168-
unsafe {
169-
T::ControlA::write(self.a);
170-
T::ControlB::write(self.b);
168+
T::ControlA::write(self.a);
169+
T::ControlB::write(self.b);
171170

172-
// Reset counter to zero
173-
T::Counter::write(0);
171+
// Reset counter to zero
172+
T::Counter::write(0);
174173

175-
if let Some(v) = self.output_compare_1 {
176-
// Set the match
177-
T::CompareA::write(v);
174+
if let Some(v) = self.output_compare_1 {
175+
// Set the match
176+
T::CompareA::write(v);
178177

179-
// Enable compare interrupt
180-
// FIXME: is this right?
181-
T::OCIEA.set_all();
182-
}
178+
// Enable compare interrupt
179+
T::OCIEA.set_all();
183180
}
184181
}
185182
}

‎src/usart.rs renamed to ‎src/modules/usart.rs

File renamed without changes.

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