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bjoernQjessebraham
bjoernQ
authored and
jessebraham
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Add DMA support for ESP32-S2
1 parent 6d769ab commit 3e4710b

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10 files changed

+185
-45
lines changed

10 files changed

+185
-45
lines changed

‎esp-hal-common/src/analog/adc/esp32s3.rs

Lines changed: 10 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -161,7 +161,11 @@ impl RegisterAccess for ADC1 {
161161

162162
fn read_done_sar() -> bool {
163163
let sensors = unsafe { &*SENS::ptr() };
164-
sensors.sar_meas1_ctrl2.read().sar_meas1_done_sar().bit_is_set()
164+
sensors
165+
.sar_meas1_ctrl2
166+
.read()
167+
.sar_meas1_done_sar()
168+
.bit_is_set()
165169
}
166170

167171
fn read_data_sar() -> u16 {
@@ -238,7 +242,11 @@ impl RegisterAccess for ADC2 {
238242

239243
fn read_done_sar() -> bool {
240244
let sensors = unsafe { &*SENS::ptr() };
241-
sensors.sar_meas2_ctrl2.read().sar_meas2_done_sar().bit_is_set()
245+
sensors
246+
.sar_meas2_ctrl2
247+
.read()
248+
.sar_meas2_done_sar()
249+
.bit_is_set()
242250
}
243251

244252
fn read_data_sar() -> u16 {

‎esp-hal-common/src/dma/mod.rs

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -7,7 +7,7 @@ use private::*;
77
#[cfg(esp32c3)]
88
pub mod gdma;
99

10-
#[cfg(esp32)]
10+
#[cfg(any(esp32, esp32s2))]
1111
pub mod pdma;
1212

1313
/// DMA Errors
@@ -62,7 +62,7 @@ pub enum DmaPeripheral {
6262
}
6363

6464
/// DMA capable peripherals
65-
#[cfg(esp32)]
65+
#[cfg(any(esp32, esp32s2))]
6666
#[derive(Clone, Copy)]
6767
pub enum DmaPeripheral {
6868
Spi2 = 0,
@@ -175,7 +175,7 @@ pub(crate) mod private {
175175
pub trait Spi2Peripheral: SpiPeripheral + PeripheralMarker {}
176176

177177
/// Marks channels as useable for SPI3
178-
#[cfg(esp32)]
178+
#[cfg(any(esp32, esp32s2))]
179179
pub trait Spi3Peripheral: SpiPeripheral + PeripheralMarker {}
180180

181181
/// DMA Rx

‎esp-hal-common/src/dma/pdma.rs

Lines changed: 17 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -13,20 +13,23 @@ macro_rules! ImplSpiChannel {
1313
impl RegisterAccess for [<Spi $num DmaChannel>] {
1414
fn init_channel() {
1515
// (only) on ESP32 we need to configure DPORT for the SPI DMA channels
16-
let dport = unsafe { &*crate::pac::DPORT::PTR };
17-
18-
match $num {
19-
2 => {
20-
dport
21-
.spi_dma_chan_sel
22-
.modify(|_, w| w.spi2_dma_chan_sel().variant(1));
23-
},
24-
3 => {
25-
dport
26-
.spi_dma_chan_sel
27-
.modify(|_, w| w.spi3_dma_chan_sel().variant(2));
28-
},
29-
_ => panic!("Only SPI2 and SPI3 supported"),
16+
#[cfg(esp32)]
17+
{
18+
let dport = unsafe { &*crate::pac::DPORT::PTR };
19+
20+
match $num {
21+
2 => {
22+
dport
23+
.spi_dma_chan_sel
24+
.modify(|_, w| w.spi2_dma_chan_sel().variant(1));
25+
},
26+
3 => {
27+
dport
28+
.spi_dma_chan_sel
29+
.modify(|_, w| w.spi3_dma_chan_sel().variant(2));
30+
},
31+
_ => panic!("Only SPI2 and SPI3 supported"),
32+
}
3033
}
3134
}
3235

‎esp-hal-common/src/lib.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -90,7 +90,7 @@ pub mod efuse;
9090
#[cfg_attr(xtensa, path = "interrupt/xtensa.rs")]
9191
pub mod interrupt;
9292

93-
#[cfg(any(esp32c3, esp32))]
93+
#[cfg(any(esp32c3, esp32, esp32s2))]
9494
pub mod dma;
9595

9696
/// Enumeration of CPU cores

‎esp-hal-common/src/spi.rs

Lines changed: 17 additions & 17 deletions
Original file line numberDiff line numberDiff line change
@@ -50,9 +50,9 @@
5050
5151
use fugit::HertzU32;
5252

53-
#[cfg(any(esp32c3, esp32))]
53+
#[cfg(any(esp32c3, esp32, esp32s2))]
5454
use crate::dma::private::{Rx, Tx};
55-
#[cfg(any(esp32c3, esp32))]
55+
#[cfg(any(esp32c3, esp32, esp32s2))]
5656
use crate::dma::{DmaError, DmaPeripheral};
5757
use crate::{
5858
clock::Clocks,
@@ -76,13 +76,13 @@ const MAX_DMA_SIZE: usize = 32736;
7676

7777
#[derive(Debug, Clone, Copy)]
7878
pub enum Error {
79-
#[cfg(any(esp32c3, esp32))]
79+
#[cfg(any(esp32c3, esp32, esp32s2))]
8080
DmaError(DmaError),
8181
MaxDmaTransferSizeExceeded,
8282
Unknown,
8383
}
8484

85-
#[cfg(any(esp32c3, esp32))]
85+
#[cfg(any(esp32c3, esp32, esp32s2))]
8686
impl From<DmaError> for Error {
8787
fn from(value: DmaError) -> Self {
8888
Error::DmaError(value)
@@ -262,16 +262,16 @@ where
262262
}
263263
}
264264

265-
#[cfg(any(esp32c3, esp32))]
265+
#[cfg(any(esp32c3, esp32, esp32s2))]
266266
pub mod dma {
267267
use core::mem;
268268

269269
use embedded_dma::{ReadBuffer, WriteBuffer};
270270

271-
#[cfg(esp32)]
271+
#[cfg(any(esp32, esp32s2))]
272272
use super::Spi3Instance;
273273
use super::{Instance, InstanceDma, Spi, Spi2Instance, MAX_DMA_SIZE};
274-
#[cfg(esp32)]
274+
#[cfg(any(esp32, esp32s2))]
275275
use crate::dma::private::Spi3Peripheral;
276276
use crate::dma::{
277277
private::{Rx, Spi2Peripheral, SpiPeripheral, Tx},
@@ -290,7 +290,7 @@ pub mod dma {
290290
fn with_dma(self, channel: Channel<TX, RX, P>) -> SpiDma<T, TX, RX, P>;
291291
}
292292

293-
#[cfg(esp32)]
293+
#[cfg(any(esp32, esp32s2))]
294294
pub trait WithDmaSpi3<T, RX, TX, P>
295295
where
296296
T: Instance + Spi3Instance,
@@ -318,7 +318,7 @@ pub mod dma {
318318
}
319319
}
320320

321-
#[cfg(esp32)]
321+
#[cfg(any(esp32, esp32s2))]
322322
impl<T, RX, TX, P> WithDmaSpi3<T, RX, TX, P> for Spi<T>
323323
where
324324
T: Instance + Spi3Instance,
@@ -916,7 +916,7 @@ mod ehal1 {
916916
}
917917
}
918918

919-
#[cfg(any(esp32c3, esp32))]
919+
#[cfg(any(esp32c3, esp32, esp32s2))]
920920
pub trait InstanceDma<TX, RX>: Instance
921921
where
922922
TX: Tx,
@@ -1065,7 +1065,7 @@ where
10651065
fn dma_peripheral(&self) -> DmaPeripheral {
10661066
match self.spi_num() {
10671067
2 => DmaPeripheral::Spi2,
1068-
#[cfg(esp32)]
1068+
#[cfg(any(esp32, esp32s2))]
10691069
3 => DmaPeripheral::Spi3,
10701070
_ => panic!("Illegal SPI instance"),
10711071
}
@@ -1078,7 +1078,7 @@ where
10781078
reg_block.dma_conf.modify(|_, w| w.dma_rx_ena().set_bit());
10791079
}
10801080

1081-
#[cfg(esp32)]
1081+
#[cfg(any(esp32, esp32s2))]
10821082
fn enable_dma(&self) {
10831083
// for non GDMA this is done in `assign_tx_device` / `assign_rx_device`
10841084
}
@@ -1100,7 +1100,7 @@ where
11001100
});
11011101
}
11021102

1103-
#[cfg(esp32)]
1103+
#[cfg(any(esp32, esp32s2))]
11041104
fn clear_dma_interrupts(&self) {
11051105
let reg_block = self.register_block();
11061106
reg_block.dma_int_clr.write(|w| {
@@ -1126,15 +1126,15 @@ where
11261126
}
11271127
}
11281128

1129-
#[cfg(any(esp32c3, esp32))]
1129+
#[cfg(any(esp32c3, esp32, esp32s2))]
11301130
impl<TX, RX> InstanceDma<TX, RX> for crate::pac::SPI2
11311131
where
11321132
TX: Tx,
11331133
RX: Rx,
11341134
{
11351135
}
11361136

1137-
#[cfg(any(esp32))]
1137+
#[cfg(any(esp32, esp32s2))]
11381138
impl<TX, RX> InstanceDma<TX, RX> for crate::pac::SPI3
11391139
where
11401140
TX: Tx,
@@ -1706,10 +1706,10 @@ impl Instance for crate::pac::SPI3 {
17061706

17071707
pub trait Spi2Instance {}
17081708

1709-
#[cfg(esp32)]
1709+
#[cfg(any(esp32, esp32s2))]
17101710
pub trait Spi3Instance {}
17111711

17121712
impl Spi2Instance for crate::pac::SPI2 {}
17131713

1714-
#[cfg(esp32)]
1714+
#[cfg(any(esp32, esp32s2))]
17151715
impl Spi3Instance for crate::pac::SPI3 {}

‎esp-hal-common/src/system.rs

Lines changed: 12 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -28,7 +28,7 @@ pub enum Peripheral {
2828
ApbSarAdc,
2929
#[cfg(esp32c3)]
3030
Gdma,
31-
#[cfg(esp32)]
31+
#[cfg(any(esp32, esp32s2))]
3232
Dma,
3333
}
3434

@@ -99,6 +99,13 @@ impl PeripheralClockControl {
9999
perip_clk_en0.modify(|_, w| w.spi_dma_clk_en().set_bit());
100100
perip_rst_en0.modify(|_, w| w.spi_dma_rst().clear_bit());
101101
}
102+
#[cfg(esp32s2)]
103+
Peripheral::Dma => {
104+
perip_clk_en0.modify(|_, w| w.spi2_dma_clk_en().set_bit());
105+
perip_rst_en0.modify(|_, w| w.spi2_dma_rst().clear_bit());
106+
perip_clk_en0.modify(|_, w| w.spi3_dma_clk_en().set_bit());
107+
perip_rst_en0.modify(|_, w| w.spi3_dma_rst().clear_bit());
108+
}
102109
}
103110
}
104111
}
@@ -113,8 +120,8 @@ pub struct CpuControl {
113120
_private: (),
114121
}
115122

116-
/// Controls the configuration of the chip's clocks.
117-
#[cfg(esp32)]
123+
/// Dummy DMA peripheral.
124+
#[cfg(any(esp32, esp32s2))]
118125
pub struct Dma {
119126
_private: (),
120127
}
@@ -125,7 +132,7 @@ pub struct SystemParts {
125132
pub peripheral_clock_control: PeripheralClockControl,
126133
pub clock_control: SystemClockControl,
127134
pub cpu_control: CpuControl,
128-
#[cfg(esp32)]
135+
#[cfg(any(esp32, esp32s2))]
129136
pub dma: Dma,
130137
}
131138

@@ -147,7 +154,7 @@ impl SystemExt for SystemPeripheral {
147154
peripheral_clock_control: PeripheralClockControl { _private: () },
148155
clock_control: SystemClockControl { _private: () },
149156
cpu_control: CpuControl { _private: () },
150-
#[cfg(esp32)]
157+
#[cfg(any(esp32, esp32s2))]
151158
dma: Dma { _private: () },
152159
}
153160
}

‎esp32s2-hal/examples/adc.rs

Lines changed: 3 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -34,14 +34,15 @@ fn main() -> ! {
3434
rtc.rwdt.disable();
3535

3636
let io = IO::new(peripherals.GPIO, peripherals.IO_MUX);
37-
//let pin3 = io.pins.gpio3.into_analog();
37+
// let pin3 = io.pins.gpio3.into_analog();
3838

3939
// Create ADC instances
4040
let analog = peripherals.SENS.split();
4141

4242
let mut adc1_config = AdcConfig::new();
4343

44-
let mut pin3 = adc1_config.enable_pin(io.pins.gpio3.into_analog(), Attenuation::Attenuation11dB);
44+
let mut pin3 =
45+
adc1_config.enable_pin(io.pins.gpio3.into_analog(), Attenuation::Attenuation11dB);
4546

4647
let mut adc1 = ADC::<ADC1>::adc(analog.adc1, adc1_config).unwrap();
4748

‎esp32s2-hal/examples/hello_world.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -40,4 +40,4 @@ fn main() -> ! {
4040
writeln!(serial0, "Hello world!").unwrap();
4141
block!(timer0.wait()).unwrap();
4242
}
43-
}
43+
}

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