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suda-morrissuda-morris
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Merge branch 'feature/reset_mcpwm_in_restart_v5.1' into 'release/v5.1'
mcpwm: reset peripheral in restart, panic and halt (v5.1) See merge request espressif/esp-idf!23651
2 parents 1d89e24 + 236d601 commit 6f459d4

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9 files changed

+187
-154
lines changed

9 files changed

+187
-154
lines changed

‎components/esp_system/include/esp_private/system_internal.h

Lines changed: 5 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -63,6 +63,11 @@ int64_t esp_system_get_time(void);
6363
*/
6464
uint32_t esp_system_get_time_resolution(void);
6565

66+
/**
67+
* @brief Before the system exit (e.g. panic, brownout, restart, etc.), this function is to be called to reset all necessary peripherals.
68+
*/
69+
void esp_system_reset_modules_on_exit(void);
70+
6671
#ifdef __cplusplus
6772
}
6873
#endif

‎components/esp_system/panic.c

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -428,6 +428,7 @@ void esp_panic_handler(panic_info_t *info)
428428
#else /* CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT || CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT */
429429
disable_all_wdts();
430430
panic_print_str("CPU halted.\r\n");
431+
esp_system_reset_modules_on_exit();
431432
while (1);
432433
#endif /* CONFIG_ESP_SYSTEM_PANIC_PRINT_REBOOT || CONFIG_ESP_SYSTEM_PANIC_SILENT_REBOOT */
433434
#endif /* CONFIG_ESP_SYSTEM_PANIC_GDBSTUB */

‎components/esp_system/port/soc/esp32/system_internal.c

Lines changed: 26 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,29 @@
2929
#include "esp32/rom/cache.h"
3030
#include "esp32/rom/rtc.h"
3131

32+
void IRAM_ATTR esp_system_reset_modules_on_exit(void)
33+
{
34+
// Flush any data left in UART FIFOs before reset the UART peripheral
35+
esp_rom_uart_tx_wait_idle(0);
36+
esp_rom_uart_tx_wait_idle(1);
37+
esp_rom_uart_tx_wait_idle(2);
38+
39+
// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
40+
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
41+
DPORT_WIFIBB_RST | DPORT_FE_RST | DPORT_WIFIMAC_RST | DPORT_BTBB_RST |
42+
DPORT_BTMAC_RST | DPORT_SDIO_RST | DPORT_SDIO_HOST_RST | DPORT_EMAC_RST |
43+
DPORT_MACPWR_RST | DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST);
44+
DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
45+
46+
// Reset timer, spi, uart, mcpwm
47+
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
48+
//UART TX FIFO cannot be reset correctly on ESP32, so reset the UART memory by DPORT here.
49+
DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST |
50+
DPORT_SPI_DMA_RST | DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST |
51+
DPORT_UART_MEM_RST | DPORT_PWM0_RST | DPORT_PWM1_RST);
52+
DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
53+
}
54+
3255
/* "inner" restart function for after RTOS, interrupts & anything else on this
3356
* core are already stopped. Stalls other core, resets hardware,
3457
* triggers restart.
@@ -73,11 +96,6 @@ void IRAM_ATTR esp_restart_noos(void)
7396
wdt_hal_disable(&wdt1_context);
7497
wdt_hal_write_protect_enable(&wdt1_context);
7598

76-
// Flush any data left in UART FIFOs
77-
esp_rom_uart_tx_wait_idle(0);
78-
esp_rom_uart_tx_wait_idle(1);
79-
esp_rom_uart_tx_wait_idle(2);
80-
8199
#ifdef CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
82100
if (esp_ptr_external_ram(esp_cpu_get_sp())) {
83101
// If stack_addr is from External Memory (CONFIG_SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY is used)
@@ -101,25 +119,8 @@ void IRAM_ATTR esp_restart_noos(void)
101119
WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
102120
WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
103121

104-
// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
105-
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_WIFIBB_RST | \
106-
DPORT_FE_RST | \
107-
DPORT_WIFIMAC_RST | \
108-
DPORT_BTBB_RST | \
109-
DPORT_BTMAC_RST | \
110-
DPORT_SDIO_RST | \
111-
DPORT_SDIO_HOST_RST | \
112-
DPORT_EMAC_RST | \
113-
DPORT_MACPWR_RST | \
114-
DPORT_RW_BTMAC_RST | \
115-
DPORT_RW_BTLP_RST);
116-
DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
117-
118-
// Reset timer/spi/uart
119-
DPORT_SET_PERI_REG_MASK(DPORT_PERIP_RST_EN_REG,
120-
//UART TX FIFO cannot be reset correctly on ESP32, so reset the UART memory by DPORT here.
121-
DPORT_TIMERS_RST | DPORT_SPI01_RST | DPORT_SPI2_RST | DPORT_SPI3_RST | DPORT_SPI_DMA_RST | DPORT_UART_RST | DPORT_UART1_RST | DPORT_UART2_RST | DPORT_UART_MEM_RST);
122-
DPORT_REG_WRITE(DPORT_PERIP_RST_EN_REG, 0);
122+
// reset necessary peripheral modules
123+
esp_system_reset_modules_on_exit();
123124

124125
// Set CPU back to XTAL source, same as hard reset. PLL keeps on to match the behavior with chips.
125126
rtc_clk_cpu_set_to_default_config();
@@ -139,7 +140,7 @@ void IRAM_ATTR esp_restart_noos(void)
139140
esp_cpu_unstall(0);
140141
esp_rom_software_reset_cpu(1);
141142
}
142-
while(true) {
143+
while (true) {
143144
;
144145
}
145146
}

‎components/esp_system/port/soc/esp32c2/system_internal.c

Lines changed: 20 additions & 14 deletions
Original file line numberDiff line numberDiff line change
@@ -27,6 +27,25 @@
2727
#include "esp32c2/rom/cache.h"
2828
#include "esp32c2/rom/rtc.h"
2929

30+
void IRAM_ATTR esp_system_reset_modules_on_exit(void)
31+
{
32+
// Flush any data left in UART FIFOs before reset the UART peripheral
33+
esp_rom_uart_tx_wait_idle(0);
34+
esp_rom_uart_tx_wait_idle(1);
35+
36+
// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
37+
38+
REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
39+
40+
// Reset timer/spi/uart
41+
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
42+
SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST);
43+
REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
44+
// Reset dma
45+
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
46+
REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);
47+
}
48+
3049
/* "inner" restart function for after RTOS, interrupts & anything else on this
3150
* core are already stopped. Stalls other core, resets hardware,
3251
* triggers restart.
@@ -52,9 +71,6 @@ void IRAM_ATTR esp_restart_noos(void)
5271
wdt_hal_disable(&wdt0_context);
5372
wdt_hal_write_protect_enable(&wdt0_context);
5473

55-
// Flush any data left in UART FIFOs
56-
esp_rom_uart_tx_wait_idle(0);
57-
esp_rom_uart_tx_wait_idle(1);
5874
// Disable cache
5975
Cache_Disable_ICache();
6076

@@ -67,17 +83,7 @@ void IRAM_ATTR esp_restart_noos(void)
6783
WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
6884
WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
6985

70-
// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
71-
72-
REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
73-
74-
// Reset timer/spi/uart
75-
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
76-
SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST);
77-
REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
78-
// Reset dma
79-
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
80-
REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);
86+
esp_system_reset_modules_on_exit();
8187

8288
// Set CPU back to XTAL source, same as hard reset. PLL keeps on to match the behavior with chips.
8389
#if !CONFIG_IDF_ENV_FPGA

‎components/esp_system/port/soc/esp32c3/system_internal.c

Lines changed: 27 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,32 @@
2828
#include "esp32c3/rom/cache.h"
2929
#include "esp32c3/rom/rtc.h"
3030

31+
void IRAM_ATTR esp_system_reset_modules_on_exit(void)
32+
{
33+
// Flush any data left in UART FIFOs before reset the UART peripheral
34+
esp_rom_uart_tx_wait_idle(0);
35+
esp_rom_uart_tx_wait_idle(1);
36+
37+
// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
38+
SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,
39+
SYSTEM_WIFIBB_RST | SYSTEM_FE_RST | SYSTEM_WIFIMAC_RST | SYSTEM_SDIO_RST |
40+
SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | SYSTEM_BTBB_RST | SYSTEM_BTBB_REG_RST |
41+
SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST | SYSTEM_RW_BTMAC_REG_RST | SYSTEM_RW_BTLP_REG_RST);
42+
REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
43+
44+
// Reset uart0 core first, then reset apb side.
45+
// rom will clear this bit, as well as SYSTEM_UART_RST
46+
SET_PERI_REG_MASK(UART_CLK_CONF_REG(0), UART_RST_CORE_M);
47+
48+
// Reset timer/spi/uart
49+
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
50+
SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST);
51+
REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
52+
// Reset dma
53+
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
54+
REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);
55+
}
56+
3157
/* "inner" restart function for after RTOS, interrupts & anything else on this
3258
* core are already stopped. Stalls other core, resets hardware,
3359
* triggers restart.
@@ -58,9 +84,6 @@ void IRAM_ATTR esp_restart_noos(void)
5884
wdt_hal_disable(&wdt1_context);
5985
wdt_hal_write_protect_enable(&wdt1_context);
6086

61-
// Flush any data left in UART FIFOs
62-
esp_rom_uart_tx_wait_idle(0);
63-
esp_rom_uart_tx_wait_idle(1);
6487
// Disable cache
6588
Cache_Disable_ICache();
6689

@@ -73,25 +96,7 @@ void IRAM_ATTR esp_restart_noos(void)
7396
WRITE_PERI_REG(GPIO_FUNC4_IN_SEL_CFG_REG, 0x30);
7497
WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
7598

76-
// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
77-
SET_PERI_REG_MASK(SYSTEM_CORE_RST_EN_REG,
78-
SYSTEM_WIFIBB_RST | SYSTEM_FE_RST | SYSTEM_WIFIMAC_RST |
79-
SYSTEM_SDIO_RST | SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST |
80-
SYSTEM_BTBB_RST | SYSTEM_BTBB_REG_RST |
81-
SYSTEM_RW_BTMAC_RST | SYSTEM_RW_BTLP_RST | SYSTEM_RW_BTMAC_REG_RST | SYSTEM_RW_BTLP_REG_RST);
82-
REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
83-
84-
// Reset uart0 core first, then reset apb side.
85-
// rom will clear this bit, as well as SYSTEM_UART_RST
86-
SET_PERI_REG_MASK(UART_CLK_CONF_REG(0), UART_RST_CORE_M);
87-
88-
// Reset timer/spi/uart
89-
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN0_REG,
90-
SYSTEM_TIMERS_RST | SYSTEM_SPI01_RST | SYSTEM_UART_RST | SYSTEM_SYSTIMER_RST);
91-
REG_WRITE(SYSTEM_PERIP_RST_EN0_REG, 0);
92-
// Reset dma
93-
SET_PERI_REG_MASK(SYSTEM_PERIP_RST_EN1_REG, SYSTEM_DMA_RST);
94-
REG_WRITE(SYSTEM_PERIP_RST_EN1_REG, 0);
99+
esp_system_reset_modules_on_exit();
95100

96101
// Set CPU back to XTAL source, same as hard reset, but keep BBPLL on so that USB Serial JTAG can log at 1st stage bootloader.
97102
#if !CONFIG_IDF_ENV_FPGA

‎components/esp_system/port/soc/esp32c6/system_internal.c

Lines changed: 31 additions & 27 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,36 @@
2828
#include "esp32c6/rom/rtc.h"
2929
#include "soc/pcr_reg.h"
3030

31+
void IRAM_ATTR esp_system_reset_modules_on_exit(void)
32+
{
33+
// Flush any data left in UART FIFOs before reset the UART peripheral
34+
esp_rom_uart_tx_wait_idle(0);
35+
esp_rom_uart_tx_wait_idle(1);
36+
37+
modem_syscon_ll_reset_all(&MODEM_SYSCON);
38+
modem_lpcon_ll_reset_all(&MODEM_LPCON);
39+
40+
// Set Peripheral clk rst
41+
SET_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
42+
SET_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
43+
SET_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
44+
SET_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
45+
SET_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
46+
SET_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
47+
SET_PERI_REG_MASK(PCR_MODEM_APB_CONF_REG, PCR_MODEM_RST_EN);
48+
SET_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
49+
50+
// Clear Peripheral clk rst
51+
CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
52+
CLEAR_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
53+
CLEAR_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
54+
CLEAR_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
55+
CLEAR_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
56+
CLEAR_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
57+
CLEAR_PERI_REG_MASK(PCR_MODEM_APB_CONF_REG, PCR_MODEM_RST_EN);
58+
CLEAR_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
59+
}
60+
3161
/* "inner" restart function for after RTOS, interrupts & anything else on this
3262
* core are already stopped. Stalls other core, resets hardware,
3363
* triggers restart.
@@ -60,9 +90,6 @@ void IRAM_ATTR esp_restart_noos(void)
6090
wdt_hal_disable(&wdt1_context);
6191
wdt_hal_write_protect_enable(&wdt1_context);
6292

63-
// Flush any data left in UART FIFOs
64-
esp_rom_uart_tx_wait_idle(0);
65-
esp_rom_uart_tx_wait_idle(1);
6693
// Disable cache
6794
Cache_Disable_ICache();
6895

@@ -73,30 +100,7 @@ void IRAM_ATTR esp_restart_noos(void)
73100
// SYSTEM_EMAC_RST | SYSTEM_MACPWR_RST | // TODO: IDF-5325 (ethernet)
74101
// REG_WRITE(SYSTEM_CORE_RST_EN_REG, 0);
75102

76-
modem_syscon_ll_reset_all(&MODEM_SYSCON);
77-
modem_lpcon_ll_reset_all(&MODEM_LPCON);
78-
79-
// Set Peripheral clk rst
80-
SET_PERI_REG_MASK(PCR_TIMERGROUP0_CONF_REG, PCR_TG0_RST_EN);
81-
SET_PERI_REG_MASK(PCR_TIMERGROUP1_CONF_REG, PCR_TG1_RST_EN);
82-
SET_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
83-
SET_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
84-
SET_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
85-
SET_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
86-
SET_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
87-
SET_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
88-
SET_PERI_REG_MASK(PCR_MODEM_APB_CONF_REG, PCR_MODEM_RST_EN);
89-
90-
// Clear Peripheral clk rst
91-
CLEAR_PERI_REG_MASK(PCR_TIMERGROUP0_CONF_REG, PCR_TG0_RST_EN);
92-
CLEAR_PERI_REG_MASK(PCR_TIMERGROUP1_CONF_REG, PCR_TG1_RST_EN);
93-
CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
94-
CLEAR_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
95-
CLEAR_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
96-
CLEAR_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
97-
CLEAR_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
98-
CLEAR_PERI_REG_MASK(PCR_SDIO_SLAVE_CONF_REG, PCR_SDIO_SLAVE_RST_EN);
99-
CLEAR_PERI_REG_MASK(PCR_MODEM_APB_CONF_REG, PCR_MODEM_RST_EN);
103+
esp_system_reset_modules_on_exit();
100104

101105
// Set CPU back to XTAL source, same as hard reset, but keep BBPLL on so that USB Serial JTAG can log at 1st stage bootloader.
102106
#if !CONFIG_IDF_ENV_FPGA

‎components/esp_system/port/soc/esp32h2/system_internal.c

Lines changed: 26 additions & 22 deletions
Original file line numberDiff line numberDiff line change
@@ -29,6 +29,31 @@
2929
#include "esp32h2/rom/rtc.h"
3030
#include "soc/pcr_reg.h"
3131

32+
void IRAM_ATTR esp_system_reset_modules_on_exit(void)
33+
{
34+
// Flush any data left in UART FIFOs before reset the UART peripheral
35+
esp_rom_uart_tx_wait_idle(0);
36+
esp_rom_uart_tx_wait_idle(1);
37+
38+
// Set Peripheral clk rst
39+
SET_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
40+
SET_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
41+
SET_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
42+
SET_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
43+
SET_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
44+
SET_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
45+
SET_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
46+
47+
// Clear Peripheral clk rst
48+
CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
49+
CLEAR_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
50+
CLEAR_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
51+
CLEAR_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
52+
CLEAR_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
53+
CLEAR_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
54+
CLEAR_PERI_REG_MASK(PCR_PWM_CONF_REG, PCR_PWM_RST_EN);
55+
}
56+
3257
/* "inner" restart function for after RTOS, interrupts & anything else on this
3358
* core are already stopped. Stalls other core, resets hardware,
3459
* triggers restart.
@@ -59,35 +84,14 @@ void IRAM_ATTR esp_restart_noos(void)
5984
wdt_hal_disable(&wdt1_context);
6085
wdt_hal_write_protect_enable(&wdt1_context);
6186

62-
// Flush any data left in UART FIFOs
63-
esp_rom_uart_tx_wait_idle(0);
64-
esp_rom_uart_tx_wait_idle(1);
6587
// Disable cache
6688
Cache_Disable_ICache();
6789

6890
// 2nd stage bootloader reconfigures SPI flash signals.
6991
// Reset them to the defaults expected by ROM.
7092
WRITE_PERI_REG(GPIO_FUNC0_IN_SEL_CFG_REG, 0x30);
7193

72-
// Set Peripheral clk rst
73-
SET_PERI_REG_MASK(PCR_TIMERGROUP0_CONF_REG, PCR_TG0_RST_EN);
74-
SET_PERI_REG_MASK(PCR_TIMERGROUP1_CONF_REG, PCR_TG1_RST_EN);
75-
SET_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
76-
SET_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
77-
SET_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
78-
SET_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
79-
SET_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
80-
SET_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
81-
82-
// Clear Peripheral clk rst
83-
CLEAR_PERI_REG_MASK(PCR_TIMERGROUP0_CONF_REG, PCR_TG0_RST_EN);
84-
CLEAR_PERI_REG_MASK(PCR_TIMERGROUP1_CONF_REG, PCR_TG1_RST_EN);
85-
CLEAR_PERI_REG_MASK(PCR_MSPI_CONF_REG, PCR_MSPI_RST_EN);
86-
CLEAR_PERI_REG_MASK(PCR_UART0_CONF_REG, PCR_UART0_RST_EN);
87-
CLEAR_PERI_REG_MASK(PCR_UART1_CONF_REG, PCR_UART1_RST_EN);
88-
CLEAR_PERI_REG_MASK(PCR_SYSTIMER_CONF_REG, PCR_SYSTIMER_RST_EN);
89-
CLEAR_PERI_REG_MASK(PCR_GDMA_CONF_REG, PCR_GDMA_RST_EN);
90-
CLEAR_PERI_REG_MASK(PCR_MODEM_CONF_REG, PCR_MODEM_RST_EN);
94+
esp_system_reset_modules_on_exit();
9195

9296
// If we set mspi clock frequency to PLL, but ROM does not have such clock source option. So reset the clock to XTAL when software restart.
9397
spi_flash_set_clock_src(MSPI_CLK_SRC_ROM_DEFAULT);

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