Merge branch 'bugfix/extram_stack_coredump_v4.4' into 'release/v4.4'

coredump: add support for stacks in external RAM (backport v4.4)

See merge request espressif/esp-idf!22391

Author: suda-morris

components/espcoredump/Kconfig

@@ -14,7 +14,6 @@ menu "Core dump"
 
         config ESP_COREDUMP_ENABLE_TO_FLASH
             bool "Flash"
-            depends on !SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
             select FREERTOS_ENABLE_TASK_SNAPSHOT
             select ESP_COREDUMP_ENABLE
         config ESP_COREDUMP_ENABLE_TO_UART
@@ -79,10 +78,21 @@ menu "Core dump"
             Config delay (in ms) before printing core dump to UART.
             Delay can be interrupted by pressing Enter key.
 
+
+    config ESP_COREDUMP_USE_STACK_SIZE
+        bool
+        default y if ESP_COREDUMP_ENABLE_TO_FLASH && SPIRAM_ALLOW_STACK_EXTERNAL_MEMORY
+        default n
+        help
+            Force the use of a custom DRAM stack for coredump when Task stacks can be in PSRAM.
+
     config ESP_COREDUMP_STACK_SIZE
         int "Reserved stack size"
         depends on ESP_COREDUMP_ENABLE
-        default 0
+        range 0 4096 if !ESP_COREDUMP_USE_STACK_SIZE
+        range 1280 4096 if ESP_COREDUMP_USE_STACK_SIZE
+        default 0 if !ESP_COREDUMP_USE_STACK_SIZE
+        default 1280 if ESP_COREDUMP_USE_STACK_SIZE
         help
             Size of the memory to be reserved for core dump stack. If 0 core dump process will run on
             the stack of crashed task/ISR, otherwise special stack will be allocated.

components/espcoredump/src/core_dump_common.c

@@ -121,7 +121,13 @@ FORCE_INLINE_ATTR void esp_core_dump_report_stack_usage(void)
     esp_core_dump_restore_sp(&s_stack_context);
 }
 
-#else
+#else // CONFIG_ESP_COREDUMP_STACK_SIZE > 0
+
+/* Here, we are not going to use a custom stack for coredump. Make sure the current configuration doesn't require one. */
+#if CONFIG_ESP_COREDUMP_USE_STACK_SIZE
+    #pragma error "CONFIG_ESP_COREDUMP_STACK_SIZE must not be 0 in the current configuration"
+#endif // ESP_COREDUMP_USE_STACK_SIZE
+
 FORCE_INLINE_ATTR void esp_core_dump_setup_stack(void)
 {
     /* If we are in ISR set watchpoint to the end of ISR stack */
@@ -139,7 +145,7 @@ FORCE_INLINE_ATTR void esp_core_dump_setup_stack(void)
 FORCE_INLINE_ATTR void esp_core_dump_report_stack_usage(void)
 {
 }
-#endif
+#endif // CONFIG_ESP_COREDUMP_STACK_SIZE > 0
 
 static void* s_exc_frame = NULL;
 

components/espcoredump/src/port/riscv/core_dump_port.c

@@ -312,10 +312,10 @@ bool esp_core_dump_check_task(core_dump_task_header_t *task)
  */
 bool esp_core_dump_mem_seg_is_sane(uint32_t addr, uint32_t sz)
 {
-    //TODO: external SRAM not supported yet
     return (esp_ptr_in_dram((void *)addr) && esp_ptr_in_dram((void *)(addr+sz-1)))
         || (esp_ptr_in_rtc_slow((void *)addr) && esp_ptr_in_rtc_slow((void *)(addr+sz-1)))
         || (esp_ptr_in_rtc_dram_fast((void *)addr) && esp_ptr_in_rtc_dram_fast((void *)(addr+sz-1)))
+        || (esp_ptr_external_ram((void *)addr) && esp_ptr_external_ram((void *)(addr+sz-1)))
         || (esp_ptr_in_iram((void *)addr) && esp_ptr_in_iram((void *)(addr+sz-1)));
 }
 

components/espcoredump/src/port/xtensa/core_dump_port.c

@@ -324,10 +324,10 @@ bool esp_core_dump_check_stack(core_dump_task_header_t *task)
  */
 bool esp_core_dump_mem_seg_is_sane(uint32_t addr, uint32_t sz)
 {
-    //TODO: external SRAM not supported yet
     return (esp_ptr_in_dram((void *)addr) && esp_ptr_in_dram((void *)(addr+sz-1)))
         || (esp_ptr_in_rtc_slow((void *)addr) && esp_ptr_in_rtc_slow((void *)(addr+sz-1)))
         || (esp_ptr_in_rtc_dram_fast((void *)addr) && esp_ptr_in_rtc_dram_fast((void *)(addr+sz-1)))
+        || (esp_ptr_external_ram((void *)addr) && esp_ptr_external_ram((void *)(addr+sz-1)))
         || (esp_ptr_in_iram((void *)addr) && esp_ptr_in_iram((void *)(addr+sz-1)));
 }
 

components/spi_flash/spi_flash_os_func_noos.c

@@ -69,8 +69,6 @@ static IRAM_ATTR esp_err_t start(void *arg)
 static IRAM_ATTR esp_err_t end(void *arg)
 {
 #if CONFIG_IDF_TARGET_ESP32
-    Cache_Flush(0);
-    Cache_Flush(1);
     Cache_Read_Enable(0);
     Cache_Read_Enable(1);
 #elif CONFIG_IDF_TARGET_ESP32S2 || CONFIG_IDF_TARGET_ESP32S3