Skip to content

Commit e08e2f0

Browse files
jack0cjack0c
committed
Merge branch 'bugfix/fix_part_of_modem_not_reset_when_power_on' into 'master'
Coexistence: fix part of modem module not reset when power up See merge request espressif/esp-idf!19849
2 parents 542bdea + 4269963 commit e08e2f0

File tree

14 files changed

+101
-62
lines changed

14 files changed

+101
-62
lines changed

‎components/esp_phy/src/phy_init.c

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -32,12 +32,9 @@
3232
#include "esp_rom_sys.h"
3333

3434
#include "soc/rtc_cntl_reg.h"
35-
#if CONFIG_IDF_TARGET_ESP32C3
36-
#include "soc/syscon_reg.h"
37-
#elif CONFIG_IDF_TARGET_ESP32S3
38-
#include "soc/syscon_reg.h"
39-
#elif CONFIG_IDF_TARGET_ESP32C2
4035
#include "soc/syscon_reg.h"
36+
#if CONFIG_IDF_TARGET_ESP32
37+
#include "soc/dport_reg.h"
4138
#endif
4239
#include "hal/efuse_hal.h"
4340

@@ -287,9 +284,12 @@ void IRAM_ATTR esp_wifi_bt_power_domain_on(void)
287284
_lock_acquire(&s_wifi_bt_pd_controller.lock);
288285
if (s_wifi_bt_pd_controller.count++ == 0) {
289286
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_PWC_REG, RTC_CNTL_WIFI_FORCE_PD);
290-
#if CONFIG_IDF_TARGET_ESP32C3 || CONFIG_IDF_TARGET_ESP32S3
291-
SET_PERI_REG_MASK(SYSCON_WIFI_RST_EN_REG, SYSTEM_WIFIBB_RST | SYSTEM_FE_RST);
292-
CLEAR_PERI_REG_MASK(SYSCON_WIFI_RST_EN_REG, SYSTEM_WIFIBB_RST | SYSTEM_FE_RST);
287+
#if CONFIG_IDF_TARGET_ESP32
288+
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, MODEM_RESET_FIELD_WHEN_PU);
289+
DPORT_CLEAR_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, MODEM_RESET_FIELD_WHEN_PU);
290+
#else
291+
SET_PERI_REG_MASK(SYSCON_WIFI_RST_EN_REG, MODEM_RESET_FIELD_WHEN_PU);
292+
CLEAR_PERI_REG_MASK(SYSCON_WIFI_RST_EN_REG, MODEM_RESET_FIELD_WHEN_PU);
293293
#endif
294294
CLEAR_PERI_REG_MASK(RTC_CNTL_DIG_ISO_REG, RTC_CNTL_WIFI_FORCE_ISO);
295295
}

‎components/esp_system/port/soc/esp32/system_internal.c

Lines changed: 11 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -101,11 +101,17 @@ void IRAM_ATTR esp_restart_noos(void)
101101
WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
102102

103103
// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
104-
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
105-
DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST |
106-
DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST |
107-
DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST |
108-
DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST);
104+
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_WIFIBB_RST | \
105+
DPORT_FE_RST | \
106+
DPORT_WIFIMAC_RST | \
107+
DPORT_BTBB_RST | \
108+
DPORT_BTMAC_RST | \
109+
DPORT_SDIO_RST | \
110+
DPORT_SDIO_HOST_RST | \
111+
DPORT_EMAC_RST | \
112+
DPORT_MACPWR_RST | \
113+
DPORT_RW_BTMAC_RST | \
114+
DPORT_RW_BTLP_RST);
109115
DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
110116

111117
// Reset timer/spi/uart

‎components/esp_system/port/soc/esp32s2/system_internal.c

Lines changed: 10 additions & 5 deletions
Original file line numberDiff line numberDiff line change
@@ -97,11 +97,16 @@ void IRAM_ATTR esp_restart_noos(void)
9797
WRITE_PERI_REG(GPIO_FUNC5_IN_SEL_CFG_REG, 0x30);
9898

9999
// Reset wifi/bluetooth/ethernet/sdio (bb/mac)
100-
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG,
101-
DPORT_BB_RST | DPORT_FE_RST | DPORT_MAC_RST |
102-
DPORT_BT_RST | DPORT_BTMAC_RST | DPORT_SDIO_RST |
103-
DPORT_SDIO_HOST_RST | DPORT_EMAC_RST | DPORT_MACPWR_RST |
104-
DPORT_RW_BTMAC_RST | DPORT_RW_BTLP_RST);
100+
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_WIFIBB_RST | \
101+
DPORT_FE_RST | \
102+
DPORT_WIFIMAC_RST | \
103+
DPORT_BTBB_RST | \
104+
DPORT_BTMAC_RST | \
105+
DPORT_SDIO_RST | \
106+
DPORT_EMAC_RST | \
107+
DPORT_MACPWR_RST | \
108+
DPORT_RW_BTMAC_RST | \
109+
DPORT_RW_BTLP_RST);
105110
DPORT_REG_WRITE(DPORT_CORE_RST_EN_REG, 0);
106111

107112
// Reset timer/spi/uart

‎components/esp_wifi/esp32/esp_adapter.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -515,8 +515,8 @@ static void IRAM_ATTR timer_arm_us_wrapper(void *ptimer, uint32_t us, bool repea
515515

516516
static void wifi_reset_mac_wrapper(void)
517517
{
518-
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_MAC_RST);
519-
DPORT_CLEAR_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_MAC_RST);
518+
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_WIFIMAC_RST);
519+
DPORT_CLEAR_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_WIFIMAC_RST);
520520
}
521521

522522
static void wifi_clock_enable_wrapper(void)

‎components/esp_wifi/esp32s2/esp_adapter.c

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -504,8 +504,8 @@ static void IRAM_ATTR timer_arm_us_wrapper(void *ptimer, uint32_t us, bool repea
504504

505505
static void wifi_reset_mac_wrapper(void)
506506
{
507-
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_MAC_RST);
508-
DPORT_CLEAR_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_MAC_RST);
507+
DPORT_SET_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_WIFIMAC_RST);
508+
DPORT_CLEAR_PERI_REG_MASK(DPORT_CORE_RST_EN_REG, DPORT_WIFIMAC_RST);
509509
}
510510

511511
static void wifi_clock_enable_wrapper(void)

‎components/soc/esp32/include/soc/dport_reg.h

Lines changed: 19 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -1065,17 +1065,25 @@
10651065
#define DPORT_CORE_RST_EN_REG (DR_REG_DPORT_BASE + 0x0D0)
10661066
/* DPORT_CORE_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
10671067
/*description: */
1068-
#define DPORT_RW_BTLP_RST (BIT(10))
1069-
#define DPORT_RW_BTMAC_RST (BIT(9))
1070-
#define DPORT_MACPWR_RST (BIT(8))
1071-
#define DPORT_EMAC_RST (BIT(7))
1072-
#define DPORT_SDIO_HOST_RST (BIT(6))
1073-
#define DPORT_SDIO_RST (BIT(5))
1074-
#define DPORT_BTMAC_RST (BIT(4))
1075-
#define DPORT_BT_RST (BIT(3))
1076-
#define DPORT_MAC_RST (BIT(2))
1077-
#define DPORT_FE_RST (BIT(1))
1078-
#define DPORT_BB_RST (BIT(0))
1068+
#define DPORT_WIFIBB_RST BIT(0)
1069+
#define DPORT_FE_RST BIT(1)
1070+
#define DPORT_WIFIMAC_RST BIT(2)
1071+
#define DPORT_BTBB_RST BIT(3)
1072+
#define DPORT_BTMAC_RST BIT(4)
1073+
#define DPORT_SDIO_RST BIT(5)
1074+
#define DPORT_SDIO_HOST_RST BIT(6)
1075+
#define DPORT_EMAC_RST BIT(7)
1076+
#define DPORT_MACPWR_RST BIT(8)
1077+
#define DPORT_RW_BTMAC_RST BIT(9)
1078+
#define DPORT_RW_BTLP_RST BIT(10)
1079+
1080+
#define MODEM_RESET_FIELD_WHEN_PU (DPORT_WIFIBB_RST | \
1081+
DPORT_FE_RST | \
1082+
DPORT_WIFIMAC_RST | \
1083+
DPORT_BTBB_RST | \
1084+
DPORT_BTMAC_RST | \
1085+
DPORT_RW_BTMAC_RST | \
1086+
DPORT_RW_BTLP_RST)
10791087

10801088
#define DPORT_BT_LPCK_DIV_INT_REG (DR_REG_DPORT_BASE + 0x0D4)
10811089
/* DPORT_BTEXTWAKEUP_REQ : R/W ;bitpos:[12] ;default: 1'b0 ; */

‎components/soc/esp32c2/include/soc/reg_base.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -14,7 +14,6 @@
1414
#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000
1515
#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000
1616
#define DR_REG_WORLD_CNTL_BASE 0x600d0000
17-
#define DR_REG_DPORT_END 0x600d3FFC
1817
#define DR_REG_UART_BASE 0x60000000
1918
#define DR_REG_SPI1_BASE 0x60002000
2019
#define DR_REG_SPI0_BASE 0x60003000

‎components/soc/esp32c3/include/soc/reg_base.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -17,7 +17,6 @@
1717
#define DR_REG_ASSIST_DEBUG_BASE 0x600ce000
1818
#define DR_REG_DEDICATED_GPIO_BASE 0x600cf000
1919
#define DR_REG_WORLD_CNTL_BASE 0x600d0000
20-
#define DR_REG_DPORT_END 0x600d3FFC
2120
#define DR_REG_UART_BASE 0x60000000
2221
#define DR_REG_SPI1_BASE 0x60002000
2322
#define DR_REG_SPI0_BASE 0x60003000

‎components/soc/esp32c3/include/soc/syscon_reg.h

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -193,6 +193,7 @@ extern "C" {
193193

194194
#define SYSTEM_CORE_RST_EN_REG SYSTEM_WIFI_RST_EN_REG
195195
#define SYSTEM_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG
196+
196197
/* SYSTEM_WIFI_RST_EN : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
197198
/*description: */
198199
#define SYSTEM_WIFIBB_RST BIT(0)
@@ -209,6 +210,17 @@ extern "C" {
209210
#define SYSTEM_RW_BTLP_REG_RST BIT(12) /* Bluetooth Low Power Registers */
210211
#define SYSTEM_BTBB_REG_RST BIT(13) /* Bluetooth Baseband Registers */
211212

213+
#define MODEM_RESET_FIELD_WHEN_PU (SYSTEM_WIFIBB_RST | \
214+
SYSTEM_FE_RST | \
215+
SYSTEM_WIFIMAC_RST | \
216+
SYSTEM_BTBB_RST | \
217+
SYSTEM_BTMAC_RST | \
218+
SYSTEM_RW_BTMAC_RST | \
219+
SYSTEM_RW_BTLP_RST | \
220+
SYSTEM_RW_BTMAC_REG_RST | \
221+
SYSTEM_RW_BTLP_REG_RST | \
222+
SYSTEM_BTBB_REG_RST)
223+
212224
#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x01C)
213225
/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
214226
/*description: */

‎components/soc/esp32s2/include/soc/reg_base.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -20,7 +20,6 @@
2020
#define DR_REG_ASSIST_DEBUG_BASE 0x3f4ce000
2121
#define DR_REG_DEDICATED_GPIO_BASE 0x3f4cf000
2222
#define DR_REG_INTRUSION_BASE 0x3f4d0000
23-
#define DR_REG_DPORT_END 0x3f4d3FFC
2423
#define DR_REG_UART_BASE 0x3f400000
2524
#define DR_REG_SPI1_BASE 0x3f402000
2625
#define DR_REG_SPI0_BASE 0x3f403000

‎components/soc/esp32s2/include/soc/syscon_reg.h

Lines changed: 25 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -1,16 +1,8 @@
1-
// Copyright 2017-2018 Espressif Systems (Shanghai) PTE LTD
2-
//
3-
// Licensed under the Apache License, Version 2.0 (the "License");
4-
// you may not use this file except in compliance with the License.
5-
// You may obtain a copy of the License at
6-
//
7-
// http://www.apache.org/licenses/LICENSE-2.0
8-
//
9-
// Unless required by applicable law or agreed to in writing, software
10-
// distributed under the License is distributed on an "AS IS" BASIS,
11-
// WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
12-
// See the License for the specific language governing permissions and
13-
// limitations under the License.
1+
/*
2+
* SPDX-FileCopyrightText: 2017-2022 Espressif Systems (Shanghai) CO LTD
3+
*
4+
* SPDX-License-Identifier: Apache-2.0
5+
*/
146
#ifndef _SOC_SYSCON_REG_H_
157
#define _SOC_SYSCON_REG_H_
168

@@ -469,23 +461,32 @@ extern "C" {
469461

470462
#define DPORT_CORE_RST_EN_REG DPORT_WIFI_RST_EN_REG
471463
#define DPORT_WIFI_RST_EN_REG SYSCON_WIFI_RST_EN_REG
464+
472465
/* DPORT_WIFI_RST : R/W ;bitpos:[31:0] ;default: 32'h0 ; */
473466
/*description: */
474467
#define DPORT_WIFI_RST 0xFFFFFFFF
475468
#define DPORT_WIFI_RST_M ((DPORT_WIFI_RST_V)<<(DPORT_WIFI_RST_S))
476469
#define DPORT_WIFI_RST_V 0xFFFFFFFF
477470
#define DPORT_WIFI_RST_S 0
478-
#define DPORT_RW_BTLP_RST (BIT(10))
479-
#define DPORT_RW_BTMAC_RST (BIT(9))
480-
#define DPORT_MACPWR_RST (BIT(8))
481-
#define DPORT_EMAC_RST (BIT(7))
482-
#define DPORT_SDIO_HOST_RST (BIT(6))
483-
#define DPORT_SDIO_RST (BIT(5))
484-
#define DPORT_BTMAC_RST (BIT(4))
485-
#define DPORT_BT_RST (BIT(3))
486-
#define DPORT_MAC_RST (BIT(2))
487-
#define DPORT_FE_RST (BIT(1))
488-
#define DPORT_BB_RST (BIT(0))
471+
472+
#define DPORT_WIFIBB_RST BIT(0)
473+
#define DPORT_FE_RST BIT(1)
474+
#define DPORT_WIFIMAC_RST BIT(2)
475+
#define DPORT_BTBB_RST BIT(3)
476+
#define DPORT_BTMAC_RST BIT(4)
477+
#define DPORT_SDIO_RST BIT(5)
478+
#define DPORT_EMAC_RST BIT(7)
479+
#define DPORT_MACPWR_RST BIT(8)
480+
#define DPORT_RW_BTMAC_RST BIT(9)
481+
#define DPORT_RW_BTLP_RST BIT(10)
482+
483+
#define MODEM_RESET_FIELD_WHEN_PU (DPORT_WIFIBB_RST | \
484+
DPORT_FE_RST | \
485+
DPORT_WIFIMAC_RST | \
486+
DPORT_BTBB_RST | \
487+
DPORT_BTMAC_RST | \
488+
DPORT_RW_BTMAC_RST | \
489+
DPORT_RW_BTLP_RST)
489490

490491
#define SYSCON_FRONT_END_MEM_PD_REG (DR_REG_SYSCON_BASE + 0x098)
491492
/* SYSCON_DC_MEM_FORCE_PD : R/W ;bitpos:[5] ;default: 1'b0 ; */

‎components/soc/esp32s3/include/soc/soc.h

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,6 @@
2525
#define DR_REG_ITAG_TABLE 0x600C6000
2626
#define DR_REG_DTAG_TABLE 0x600C8000
2727
#define DR_REG_EXT_MEM_ENC 0x600CC000
28-
#define DR_REG_DPORT_END 0x600D3FFC
2928

3029

3130
#define REG_UHCI_BASE(i) (DR_REG_UHCI0_BASE - (i) * 0x8000)

‎components/soc/esp32s3/include/soc/syscon_reg.h

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -199,6 +199,7 @@ extern "C" {
199199
#define SYSTEM_WIFI_RST_M ((SYSTEM_WIFI_RST_V) << (SYSTEM_WIFI_RST_S))
200200
#define SYSTEM_WIFI_RST_V 0xFFFFFFFF
201201
#define SYSTEM_WIFI_RST_S 0
202+
202203
#define SYSTEM_WIFIBB_RST BIT(0)
203204
#define SYSTEM_FE_RST BIT(1)
204205
#define SYSTEM_WIFIMAC_RST BIT(2)
@@ -213,6 +214,17 @@ extern "C" {
213214
#define SYSTEM_RW_BTLP_REG_RST BIT(12) /* Bluetooth Low Power Registers */
214215
#define SYSTEM_BTBB_REG_RST BIT(13) /* Bluetooth Baseband Registers */
215216

217+
#define MODEM_RESET_FIELD_WHEN_PU (SYSTEM_WIFIBB_RST | \
218+
SYSTEM_FE_RST | \
219+
SYSTEM_WIFIMAC_RST | \
220+
SYSTEM_BTBB_RST | \
221+
SYSTEM_BTMAC_RST | \
222+
SYSTEM_RW_BTMAC_RST | \
223+
SYSTEM_RW_BTLP_RST | \
224+
SYSTEM_RW_BTMAC_REG_RST | \
225+
SYSTEM_RW_BTLP_REG_RST | \
226+
SYSTEM_BTBB_REG_RST)
227+
216228
#define SYSCON_HOST_INF_SEL_REG (DR_REG_SYSCON_BASE + 0x1C)
217229
/* SYSCON_PERI_IO_SWAP : R/W ;bitpos:[7:0] ;default: 8'h0 ; */
218230
/*description: .*/

‎tools/ci/check_copyright_ignore.txt

Lines changed: 0 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1108,7 +1108,6 @@ components/soc/esp32s2/include/soc/soc_ulp.h
11081108
components/soc/esp32s2/include/soc/spi_mem_reg.h
11091109
components/soc/esp32s2/include/soc/spi_pins.h
11101110
components/soc/esp32s2/include/soc/spi_reg.h
1111-
components/soc/esp32s2/include/soc/syscon_reg.h
11121111
components/soc/esp32s2/include/soc/systimer_reg.h
11131112
components/soc/esp32s2/include/soc/systimer_struct.h
11141113
components/soc/esp32s2/include/soc/touch_sensor_channel.h

0 commit comments

Comments
 (0)