@@ -7485,6 +7485,8 @@ static void ggml_cuda_op_dequantize_mul_mat_vec(
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const int64_t ne00 = src0->ne [0 ];
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const int64_t row_diff = row_high - row_low;
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+ GGML_ASSERT (src1->type == GGML_TYPE_F32);
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+
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// on some GPUs it is faster to convert src1 to half and to use half precision intrinsics
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#ifdef GGML_CUDA_F16
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cuda_pool_alloc<half> src1_dfloat_a;
@@ -7577,6 +7579,7 @@ static void ggml_cuda_op_mul_mat_cublas(
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const int compute_capability = g_device_caps[id].cc ;
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if (compute_capability >= CC_VOLTA && (src0->type == GGML_TYPE_F16 || ggml_is_quantized (src0->type )) && ggml_is_contiguous (src0) && row_diff == src0->ne [1 ] && dst->op_params [0 ] == GGML_PREC_DEFAULT) {
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+ // printf("this branch\n");
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// convert src0 and src1 to fp16, multiply as fp16, convert dst to fp32
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cuda_pool_alloc<half> src0_as_f16;
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if (src0->type != GGML_TYPE_F16) {
@@ -8043,6 +8046,7 @@ static void ggml_cuda_op_mul_mat(
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GGML_ASSERT (dst->backend != GGML_BACKEND_GPU_SPLIT);
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GGML_ASSERT (src1->backend != GGML_BACKEND_GPU_SPLIT);
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+ GGML_ASSERT (src1->type == GGML_TYPE_F32 || (src1->ne [2 ] == 1 && src1->ne [3 ] == 1 ));
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GGML_ASSERT (ne12 >= ne02 && ne12 % ne02 == 0 );
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@@ -8489,9 +8493,9 @@ static __global__ void k_compute_batched_ptrs(
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int64_t i03 = i13 / r3;
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int64_t i02 = i12 / r2;
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- ptrs_src[0 *ne23 + i12 + i13*ne12] = (const char *) src0_as_f16 + i02*nb02 + i03*nb03;
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- ptrs_src[1 *ne23 + i12 + i13*ne12] = (const char *) src1_as_f16 + i12*nb12/ 2 + i13*nb13/ 2 ;
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- ptrs_dst[0 *ne23 + i12 + i13*ne12] = ( char *) dst + i12*nbd2 + i13*nbd3;
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+ ptrs_src[0 *ne23 + i12 + i13*ne12] = (const char *) src0_as_f16 + i02*nb02 + i03*nb03;
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+ ptrs_src[1 *ne23 + i12 + i13*ne12] = (const char *) src1_as_f16 + i12*nb12 + i13*nb13;
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+ ptrs_dst[0 *ne23 + i12 + i13*ne12] = ( char *) dst + i12*nbd2 + i13*nbd3;
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}
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static void ggml_cuda_mul_mat_mat_batched_cublas (const ggml_tensor * src0, const ggml_tensor * src1, ggml_tensor * dst) {
@@ -8500,28 +8504,10 @@ static void ggml_cuda_mul_mat_mat_batched_cublas(const ggml_tensor * src0, const
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GGML_ASSERT (src0->backend != GGML_BACKEND_GPU_SPLIT);
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GGML_ASSERT (src0->type == GGML_TYPE_F16);
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- GGML_ASSERT (src1->type == GGML_TYPE_F32);
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-
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- const int64_t ne00 = src0->ne [0 ]; GGML_UNUSED (ne00);
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- const int64_t ne01 = src0->ne [1 ];
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- const int64_t ne02 = src0->ne [2 ];
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- const int64_t ne03 = src0->ne [3 ];
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-
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- const int64_t nb01 = src0->nb [1 ];
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- const int64_t nb02 = src0->nb [2 ]; GGML_UNUSED (nb02);
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- const int64_t nb03 = src0->nb [3 ]; GGML_UNUSED (nb03);
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-
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- const int64_t ne10 = src1->ne [0 ];
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- const int64_t ne11 = src1->ne [1 ];
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- const int64_t ne12 = src1->ne [2 ];
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- const int64_t ne13 = src1->ne [3 ];
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- const int64_t nb11 = src1->nb [1 ];
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- const int64_t nb12 = src1->nb [2 ]; GGML_UNUSED (nb12);
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- const int64_t nb13 = src1->nb [3 ]; GGML_UNUSED (nb13);
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+ GGML_TENSOR_BINARY_OP_LOCALS
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- const int64_t ne1 = ggml_nelements (src1);
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- const int64_t ne = ggml_nelements (dst);
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+ const int64_t ne_dst = ggml_nelements (dst);
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ggml_cuda_set_device (g_main_device);
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cudaStream_t main_stream = g_cudaStreams[g_main_device][0 ];
@@ -8530,7 +8516,7 @@ static void ggml_cuda_mul_mat_mat_batched_cublas(const ggml_tensor * src0, const
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ggml_tensor_extra_gpu * src0_extra = (ggml_tensor_extra_gpu *) src0->extra ;
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void * src0_ddq = src0_extra->data_device [g_main_device];
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- half * src0_as_f16 = (half *) src0_ddq;
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+ half * src0_f16 = (half *) src0_ddq;
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ggml_tensor_extra_gpu * src1_extra = (ggml_tensor_extra_gpu *) src1->extra ;
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float * src1_ddf = (float *) src1_extra->data_device [g_main_device];
@@ -8539,11 +8525,15 @@ static void ggml_cuda_mul_mat_mat_batched_cublas(const ggml_tensor * src0, const
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float * dst_ddf = (float *) dst_extra->data_device [g_main_device];
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// convert src1 to fp16
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- const to_fp16_cuda_t to_fp16_cuda = ggml_get_to_fp16_cuda (src1->type );
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- GGML_ASSERT (to_fp16_cuda != nullptr );
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-
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- cuda_pool_alloc<half> src1_as_f16 (ne1);
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- to_fp16_cuda (src1_ddf, src1_as_f16.get (), ne1, main_stream);
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+ cuda_pool_alloc<half> src1_f16_alloc;
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+ if (src1->type != GGML_TYPE_F16) {
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+ const to_fp16_cuda_t to_fp16_cuda = ggml_get_to_fp16_cuda (src1->type );
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+ const int64_t ne_src1 = ggml_nelements (src1);
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+ src1_f16_alloc.alloc (ne_src1);
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+ GGML_ASSERT (to_fp16_cuda != nullptr );
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+ to_fp16_cuda (src1_ddf, src1_f16_alloc.get (), ne_src1, main_stream);
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+ }
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+ half * src1_f16 = src1->type == GGML_TYPE_F16 ? (half *) src1_ddf : src1_f16_alloc.get ();
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cuda_pool_alloc<half> dst_f16;
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char * dst_t ;
@@ -8565,7 +8555,7 @@ static void ggml_cuda_mul_mat_mat_batched_cublas(const ggml_tensor * src0, const
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const void * beta = &beta_f16;
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if (dst->op_params [0 ] == GGML_PREC_DEFAULT) {
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- dst_t = (char *) dst_f16.alloc (ne );
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+ dst_t = (char *) dst_f16.alloc (ne_dst );
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nbd2 /= sizeof (float ) / sizeof (half);
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nbd3 /= sizeof (float ) / sizeof (half);
@@ -8612,9 +8602,9 @@ static void ggml_cuda_mul_mat_mat_batched_cublas(const ggml_tensor * src0, const
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CUBLAS_CHECK (
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cublasGemmStridedBatchedEx (g_cublas_handles[g_main_device], CUBLAS_OP_T, CUBLAS_OP_N,
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ne01, ne11, ne10,
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- alpha, (const char *) src0_as_f16, CUDA_R_16F, nb01/sizeof (half), src0-> nb [ 2 ]/ sizeof (half) , // strideA
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- (const char *) src1_as_f16. get () , CUDA_R_16F, nb11/sizeof ( float ), src1-> nb [ 2 ]/ sizeof ( float ), // strideB
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- beta, ( char *) dst_t , cu_data_type, ne01, dst-> nb [ 2 ]/ sizeof ( float ), // strideC
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+ alpha, (const char *) src0_f16, CUDA_R_16F, nb01/nb00, nb02/nb00 , // strideA
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+ (const char *) src1_f16 , CUDA_R_16F, nb11/nb10, nb12/nb10, // strideB
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+ beta, ( char *) dst_t , cu_data_type, ne01, nb2/nb0, // strideC
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ne12*ne13,
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cu_compute_type,
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CUBLAS_GEMM_DEFAULT_TENSOR_OP));
@@ -8627,21 +8617,22 @@ static void ggml_cuda_mul_mat_mat_batched_cublas(const ggml_tensor * src0, const
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dim3 block_dims (ne13, ne12);
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k_compute_batched_ptrs<<<1 , block_dims, 0 , main_stream>>> (
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- src0_as_f16, src1_as_f16. get () , dst_t ,
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+ src0_f16, src1_f16 , dst_t ,
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ptrs_src.get (), ptrs_dst.get (),
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ne12, ne13,
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ne23,
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nb02, nb03,
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- nb12, nb13,
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+ src1->type == GGML_TYPE_F16 ? nb12 : nb12/2 ,
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+ src1->type == GGML_TYPE_F16 ? nb13 : nb13/2 ,
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nbd2, nbd3,
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r2, r3);
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CUDA_CHECK (cudaGetLastError ());
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CUBLAS_CHECK (
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cublasGemmBatchedEx (g_cublas_handles[g_main_device], CUBLAS_OP_T, CUBLAS_OP_N,
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ne01, ne11, ne10,
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- alpha, (const void **) (ptrs_src.get () + 0 *ne23), CUDA_R_16F, nb01/sizeof (half) ,
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- (const void **) (ptrs_src.get () + 1 *ne23), CUDA_R_16F, nb11/sizeof ( float ) ,
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+ alpha, (const void **) (ptrs_src.get () + 0 *ne23), CUDA_R_16F, nb01/nb00 ,
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+ (const void **) (ptrs_src.get () + 1 *ne23), CUDA_R_16F, nb11/nb10 ,
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beta, ( void **) (ptrs_dst.get () + 0 *ne23), cu_data_type, ne01,
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ne23,
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cu_compute_type,
@@ -8651,7 +8642,7 @@ static void ggml_cuda_mul_mat_mat_batched_cublas(const ggml_tensor * src0, const
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if (dst->op_params [0 ] == GGML_PREC_DEFAULT) {
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const to_fp32_cuda_t to_fp32_cuda = ggml_get_to_fp32_cuda (GGML_TYPE_F16);
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- to_fp32_cuda (dst_f16.get (), dst_ddf, ne , main_stream);
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+ to_fp32_cuda (dst_f16.get (), dst_ddf, ne_dst , main_stream);
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}
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}
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@@ -8690,13 +8681,13 @@ static void ggml_cuda_mul_mat(const ggml_tensor * src0, const ggml_tensor * src1
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} else if (!split && all_on_device && !use_tensor_cores && src0->type == GGML_TYPE_F16 && !ggml_is_contiguous (src0) && !ggml_is_transposed (src1) && src1->ne [1 ] == 1 ) {
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// KQV single-batch
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ggml_cuda_mul_mat_vec_nc (src0, src1, dst);
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- } else if (!split && all_on_device && use_tensor_cores && src0->type == GGML_TYPE_F16 && src1-> type == GGML_TYPE_F32 && !ggml_is_transposed (src0) && !ggml_is_transposed (src1)) {
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+ } else if (!split && all_on_device && use_tensor_cores && src0->type == GGML_TYPE_F16 && !ggml_is_transposed (src0) && !ggml_is_transposed (src1)) {
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// KQ + KQV multi-batch
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ggml_cuda_mul_mat_mat_batched_cublas (src0, src1, dst);
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} else if (src0->type == GGML_TYPE_F32) {
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ggml_cuda_op_mul_mat (src0, src1, dst, ggml_cuda_op_mul_mat_cublas, false );
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} else if (ggml_is_quantized (src0->type ) || src0->type == GGML_TYPE_F16) {
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- if (src1->ne [1 ] == 1 && src0->ne [0 ] % GGML_CUDA_DMMV_X == 0 ) {
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+ if (src1->ne [1 ] == 1 && src0->ne [0 ] % GGML_CUDA_DMMV_X == 0 && src1-> type == GGML_TYPE_F32 ) {
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#ifdef GGML_CUDA_FORCE_DMMV
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const bool use_mul_mat_vec_q = false ;
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#else
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