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cmd/internal/obj/riscv: fix vector integer multiply add
The RISC-V integer vector multiply add instructions are not encoded correctly; the first and second arguments are swapped. For example, the instruction VMACCVV V1, V2, V3 encodes to b620a1d7 or vmacc.vv v3,v1,v2 and not b61121d7 or vmacc.vv v3,v2,v1 as expected. This is inconsistent with the argument ordering we use for 3 argument vector instructions, in which the argument order, as given in the RISC-V specifications, is reversed, and also with the vector FMA instructions which have the same argument ordering as the vector integer multiply add instructions in the "The RISC-V Instruction Set Manual Volume I". For example, in the ISA manual we have the following instruction definitions ; Integer multiply-add, overwrite addend vmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] ; FP multiply-accumulate, overwrites addend vfmacc.vv vd, vs1, vs2, vm # vd[i] = +(vs1[i] * vs2[i]) + vd[i] It's reasonable to expect that the Go assembler would use the same argument ordering for both of these instructions. It currently does not. We fix the issue by switching the argument ordering for the vector integer multiply add instructions to match those of the vector FMA instructions. Change-Id: Ib98e9999617f991969e5c831734b3bb3324439f6 Reviewed-on: https://go-review.googlesource.com/c/go/+/670335 Reviewed-by: Carlos Amedee <[email protected]> LUCI-TryBot-Result: Go LUCI <[email protected]> Reviewed-by: Meng Zhuo <[email protected]> Reviewed-by: Cherry Mui <[email protected]>
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‎src/cmd/asm/internal/asm/testdata/riscv64.s

Lines changed: 30 additions & 30 deletions
Original file line numberDiff line numberDiff line change
@@ -830,38 +830,38 @@ start:
830830
VWMULSUVX X10, V2, V0, V3 // d76125e8
831831

832832
// 31.11.13: Vector Single-Width Integer Multiply-Add Instructions
833-
VMACCVV V1, V2, V3 // d7a120b6
834-
VMACCVV V1, V2, V0, V3 // d7a120b4
835-
VMACCVX X10, V2, V3 // d76125b6
836-
VMACCVX X10, V2, V0, V3 // d76125b4
837-
VNMSACVV V1, V2, V3 // d7a120be
838-
VNMSACVV V1, V2, V0, V3 // d7a120bc
839-
VNMSACVX X10, V2, V3 // d76125be
840-
VNMSACVX X10, V2, V0, V3 // d76125bc
841-
VMADDVV V1, V2, V3 // d7a120a6
842-
VMADDVV V1, V2, V0, V3 // d7a120a4
843-
VMADDVX X10, V2, V3 // d76125a6
844-
VMADDVX X10, V2, V0, V3 // d76125a4
845-
VNMSUBVV V1, V2, V3 // d7a120ae
846-
VNMSUBVV V1, V2, V0, V3 // d7a120ac
847-
VNMSUBVX X10, V2, V3 // d76125ae
848-
VNMSUBVX X10, V2, V0, V3 // d76125ac
833+
VMACCVV V2, V1, V3 // d7a120b6
834+
VMACCVV V2, V1, V0, V3 // d7a120b4
835+
VMACCVX V2, X10, V3 // d76125b6
836+
VMACCVX V2, X10, V0, V3 // d76125b4
837+
VNMSACVV V2, V1, V3 // d7a120be
838+
VNMSACVV V2, V1, V0, V3 // d7a120bc
839+
VNMSACVX V2, X10, V3 // d76125be
840+
VNMSACVX V2, X10, V0, V3 // d76125bc
841+
VMADDVV V2, V1, V3 // d7a120a6
842+
VMADDVV V2, V1, V0, V3 // d7a120a4
843+
VMADDVX V2, X10, V3 // d76125a6
844+
VMADDVX V2, X10, V0, V3 // d76125a4
845+
VNMSUBVV V2, V1, V3 // d7a120ae
846+
VNMSUBVV V2, V1, V0, V3 // d7a120ac
847+
VNMSUBVX V2, X10, V3 // d76125ae
848+
VNMSUBVX V2, X10, V0, V3 // d76125ac
849849

850850
// 31.11.14: Vector Widening Integer Multiply-Add Instructions
851-
VWMACCUVV V1, V2, V3 // d7a120f2
852-
VWMACCUVV V1, V2, V0, V3 // d7a120f0
853-
VWMACCUVX X10, V2, V3 // d76125f2
854-
VWMACCUVX X10, V2, V0, V3 // d76125f0
855-
VWMACCVV V1, V2, V3 // d7a120f6
856-
VWMACCVV V1, V2, V0, V3 // d7a120f4
857-
VWMACCVX X10, V2, V3 // d76125f6
858-
VWMACCVX X10, V2, V0, V3 // d76125f4
859-
VWMACCSUVV V1, V2, V3 // d7a120fe
860-
VWMACCSUVV V1, V2, V0, V3 // d7a120fc
861-
VWMACCSUVX X10, V2, V3 // d76125fe
862-
VWMACCSUVX X10, V2, V0, V3 // d76125fc
863-
VWMACCUSVX X10, V2, V3 // d76125fa
864-
VWMACCUSVX X10, V2, V0, V3 // d76125f8
851+
VWMACCUVV V2, V1, V3 // d7a120f2
852+
VWMACCUVV V2, V1, V0, V3 // d7a120f0
853+
VWMACCUVX V2, X10, V3 // d76125f2
854+
VWMACCUVX V2, X10, V0, V3 // d76125f0
855+
VWMACCVV V2, V1, V3 // d7a120f6
856+
VWMACCVV V2, V1, V0, V3 // d7a120f4
857+
VWMACCVX V2, X10, V3 // d76125f6
858+
VWMACCVX V2, X10, V0, V3 // d76125f4
859+
VWMACCSUVV V2, V1, V3 // d7a120fe
860+
VWMACCSUVV V2, V1, V0, V3 // d7a120fc
861+
VWMACCSUVX V2, X10, V3 // d76125fe
862+
VWMACCSUVX V2, X10, V0, V3 // d76125fc
863+
VWMACCUSVX V2, X10, V3 // d76125fa
864+
VWMACCUSVX V2, X10, V0, V3 // d76125f8
865865

866866
// 31.11.15: Vector Integer Merge Instructions
867867
VMERGEVVM V1, V2, V0, V3 // d781205c

‎src/cmd/asm/internal/asm/testdata/riscv64validation.s

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -214,19 +214,19 @@ TEXT validation(SB),$0
214214
VWMULUVX V1, V2, V3 // ERROR "expected integer register in rs1 position"
215215
VWMULSUVV X10, V2, V3 // ERROR "expected vector register in vs1 position"
216216
VWMULSUVX V1, V2, V3 // ERROR "expected integer register in rs1 position"
217-
VMACCVV X10, V2, V3 // ERROR "expected vector register in vs1 position"
217+
VMACCVV V2, X10, V3 // ERROR "expected vector register in vs1 position"
218218
VMACCVX V1, V2, V3 // ERROR "expected integer register in rs1 position"
219-
VNMSACVV X10, V2, V3 // ERROR "expected vector register in vs1 position"
219+
VNMSACVV V2, X10, V3 // ERROR "expected vector register in vs1 position"
220220
VNMSACVX V1, V2, V3 // ERROR "expected integer register in rs1 position"
221-
VMADDVV X10, V2, V3 // ERROR "expected vector register in vs1 position"
221+
VMADDVV V2, X10, V3 // ERROR "expected vector register in vs1 position"
222222
VMADDVX V1, V2, V3 // ERROR "expected integer register in rs1 position"
223-
VNMSUBVV X10, V2, V3 // ERROR "expected vector register in vs1 position"
223+
VNMSUBVV V2, X10, V3 // ERROR "expected vector register in vs1 position"
224224
VNMSUBVX V1, V2, V3 // ERROR "expected integer register in rs1 position"
225-
VWMACCUVV X10, V2, V3 // ERROR "expected vector register in vs1 position"
225+
VWMACCUVV V2, X10, V3 // ERROR "expected vector register in vs1 position"
226226
VWMACCUVX V1, V2, V3 // ERROR "expected integer register in rs1 position"
227-
VWMACCVV X10, V2, V3 // ERROR "expected vector register in vs1 position"
227+
VWMACCVV V2, X10, V3 // ERROR "expected vector register in vs1 position"
228228
VWMACCVX V1, V2, V3 // ERROR "expected integer register in rs1 position"
229-
VWMACCSUVV X10, V2, V3 // ERROR "expected vector register in vs1 position"
229+
VWMACCSUVV V2, X10, V3 // ERROR "expected vector register in vs1 position"
230230
VWMACCSUVX V1, V2, V3 // ERROR "expected integer register in rs1 position"
231231
VWMACCUSVX V1, V2, V3 // ERROR "expected integer register in rs1 position"
232232
VMERGEVVM X10, V2, V0, V3 // ERROR "expected vector register in vs1 position"

‎src/cmd/internal/obj/riscv/obj.go

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -3697,8 +3697,6 @@ func instructionsForProg(p *obj.Prog) []*instruction {
36973697
AVMULVV, AVMULVX, AVMULHVV, AVMULHVX, AVMULHUVV, AVMULHUVX, AVMULHSUVV, AVMULHSUVX,
36983698
AVDIVUVV, AVDIVUVX, AVDIVVV, AVDIVVX, AVREMUVV, AVREMUVX, AVREMVV, AVREMVX,
36993699
AVWMULVV, AVWMULVX, AVWMULUVV, AVWMULUVX, AVWMULSUVV, AVWMULSUVX, AVNSRLWV, AVNSRLWX, AVNSRAWV, AVNSRAWX,
3700-
AVMACCVV, AVMACCVX, AVNMSACVV, AVNMSACVX, AVMADDVV, AVMADDVX, AVNMSUBVV, AVNMSUBVX,
3701-
AVWMACCUVV, AVWMACCUVX, AVWMACCVV, AVWMACCVX, AVWMACCSUVV, AVWMACCSUVX, AVWMACCUSVX,
37023700
AVSADDUVV, AVSADDUVX, AVSADDUVI, AVSADDVV, AVSADDVX, AVSADDVI, AVSSUBUVV, AVSSUBUVX, AVSSUBVV, AVSSUBVX,
37033701
AVAADDUVV, AVAADDUVX, AVAADDVV, AVAADDVX, AVASUBUVV, AVASUBUVX, AVASUBVV, AVASUBVX,
37043702
AVSMULVV, AVSMULVX, AVSSRLVV, AVSSRLVX, AVSSRLVI, AVSSRAVV, AVSSRAVX, AVSSRAVI,
@@ -3724,7 +3722,9 @@ func instructionsForProg(p *obj.Prog) []*instruction {
37243722

37253723
case AVFMACCVV, AVFMACCVF, AVFNMACCVV, AVFNMACCVF, AVFMSACVV, AVFMSACVF, AVFNMSACVV, AVFNMSACVF,
37263724
AVFMADDVV, AVFMADDVF, AVFNMADDVV, AVFNMADDVF, AVFMSUBVV, AVFMSUBVF, AVFNMSUBVV, AVFNMSUBVF,
3727-
AVFWMACCVV, AVFWMACCVF, AVFWNMACCVV, AVFWNMACCVF, AVFWMSACVV, AVFWMSACVF, AVFWNMSACVV, AVFWNMSACVF:
3725+
AVFWMACCVV, AVFWMACCVF, AVFWNMACCVV, AVFWNMACCVF, AVFWMSACVV, AVFWMSACVF, AVFWNMSACVV, AVFWNMSACVF,
3726+
AVMACCVV, AVMACCVX, AVNMSACVV, AVNMSACVX, AVMADDVV, AVMADDVX, AVNMSUBVV, AVNMSUBVX,
3727+
AVWMACCUVV, AVWMACCUVX, AVWMACCVV, AVWMACCVX, AVWMACCSUVV, AVWMACCSUVX, AVWMACCUSVX:
37283728
switch {
37293729
case ins.rs3 == obj.REG_NONE:
37303730
ins.funct7 |= 1 // unmasked

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