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[RISCV] Add Andes N45/NX45 processor definition (llvm#136670)
Andes N45/NX45 are 32/64bit in-order dual-issue 8-stage pipeline CPU architecture implementing the RV[32|64]IMAFDC_Zba_Zbb_Zbs ISA extensions. They are developed by Andes Technology https://www.andestech.com, a RISC-V IP provider. The overviews for N45/NX45: https://www.andestech.com/en/products-solutions/andescore-processors/riscv-n45/ https://www.andestech.com/en/products-solutions/andescore-processors/riscv-nx45/ Scheduling model will be implemented in a later PR.
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‎clang/test/Driver/riscv-cpus.c

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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=syntacore-scr7 | FileCheck -check-prefix=MTUNE-SYNTACORE-SCR7 %s
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// MTUNE-SYNTACORE-SCR7: "-tune-cpu" "syntacore-scr7"
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// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mcpu=andes-n45 | FileCheck -check-prefix=MCPU-ANDES-N45 %s
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// MCPU-ANDES-N45: "-target-cpu" "andes-n45"
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// MCPU-ANDES-N45-SAME: "-target-feature" "+m"
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// MCPU-ANDES-N45-SAME: "-target-feature" "+a"
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// MCPU-ANDES-N45-SAME: "-target-feature" "+f"
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// MCPU-ANDES-N45-SAME: "-target-feature" "+d"
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// MCPU-ANDES-N45-SAME: "-target-feature" "+c"
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// MCPU-ANDES-N45-SAME: "-target-feature" "+zicsr"
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// MCPU-ANDES-N45-SAME: "-target-feature" "+zifencei"
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// MCPU-ANDES-N45-SAME: "-target-feature" "+zba"
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// MCPU-ANDES-N45-SAME: "-target-feature" "+zbb"
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// MCPU-ANDES-N45-SAME: "-target-feature" "+zbs"
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// MCPU-ANDES-N45-SAME: "-target-abi" "ilp32d"
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// RUN: %clang --target=riscv32 -### -c %s 2>&1 -mtune=andes-n45 | FileCheck -check-prefix=MTUNE-ANDES-N45 %s
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// MTUNE-ANDES-N45: "-tune-cpu" "andes-n45"
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mcpu=andes-nx45 | FileCheck -check-prefix=MCPU-ANDES-NX45 %s
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// MCPU-ANDES-NX45: "-target-cpu" "andes-nx45"
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// MCPU-ANDES-NX45-SAME: "-target-feature" "+m"
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// MCPU-ANDES-NX45-SAME: "-target-feature" "+a"
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// MCPU-ANDES-NX45-SAME: "-target-feature" "+f"
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// MCPU-ANDES-NX45-SAME: "-target-feature" "+d"
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// MCPU-ANDES-NX45-SAME: "-target-feature" "+c"
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// MCPU-ANDES-NX45-SAME: "-target-feature" "+zicsr"
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// MCPU-ANDES-NX45-SAME: "-target-feature" "+zifencei"
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// MCPU-ANDES-NX45-SAME: "-target-feature" "+zba"
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// MCPU-ANDES-NX45-SAME: "-target-feature" "+zbb"
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// MCPU-ANDES-NX45-SAME: "-target-feature" "+zbs"
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// MCPU-ANDES-NX45-SAME: "-target-abi" "lp64d"
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// RUN: %clang --target=riscv64 -### -c %s 2>&1 -mtune=andes-nx45 | FileCheck -check-prefix=MTUNE-ANDES-NX45 %s
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// MTUNE-ANDES-NX45: "-tune-cpu" "andes-nx45"

‎clang/test/Misc/target-invalid-cpu-note/riscv.c

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// RUN: not %clang_cc1 -triple riscv32 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV32
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// RISCV32: error: unknown target CPU 'not-a-cpu'
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// RISCV32-NEXT: note: valid target CPU values are:
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// RISCV32-SAME: {{^}} generic-rv32
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// RISCV32-SAME: {{^}} andes-n45
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// RISCV32-SAME: {{^}}, generic-rv32
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// RISCV32-SAME: {{^}}, rocket-rv32
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// RISCV32-SAME: {{^}}, rp2350-hazard3
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// RISCV32-SAME: {{^}}, sifive-e20
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// RUN: not %clang_cc1 -triple riscv64 -target-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix RISCV64
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// RISCV64: error: unknown target CPU 'not-a-cpu'
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// RISCV64-NEXT: note: valid target CPU values are:
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// RISCV64-SAME: {{^}} generic-rv64
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// RISCV64-SAME: {{^}} andes-nx45
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// RISCV64-SAME: {{^}}, generic-rv64
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// RISCV64-SAME: {{^}}, mips-p8700
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// RISCV64-SAME: {{^}}, rocket-rv64
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// RISCV64-SAME: {{^}}, sifive-p450
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// RUN: not %clang_cc1 -triple riscv32 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV32
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// TUNE-RISCV32: error: unknown target CPU 'not-a-cpu'
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// TUNE-RISCV32-NEXT: note: valid target CPU values are:
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// TUNE-RISCV32-SAME: {{^}} generic-rv32
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// TUNE-RISCV32-SAME: {{^}} andes-n45
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// TUNE-RISCV32-SAME: {{^}}, generic-rv32
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// TUNE-RISCV32-SAME: {{^}}, rocket-rv32
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// TUNE-RISCV32-SAME: {{^}}, rp2350-hazard3
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// TUNE-RISCV32-SAME: {{^}}, sifive-e20
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// RUN: not %clang_cc1 -triple riscv64 -tune-cpu not-a-cpu -fsyntax-only %s 2>&1 | FileCheck %s --check-prefix TUNE-RISCV64
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// TUNE-RISCV64: error: unknown target CPU 'not-a-cpu'
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// TUNE-RISCV64-NEXT: note: valid target CPU values are:
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// TUNE-RISCV64-SAME: {{^}} generic-rv64
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// TUNE-RISCV64-SAME: {{^}} andes-nx45
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// TUNE-RISCV64-SAME: {{^}}, generic-rv64
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// TUNE-RISCV64-SAME: {{^}}, mips-p8700
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// TUNE-RISCV64-SAME: {{^}}, rocket-rv64
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// TUNE-RISCV64-SAME: {{^}}, sifive-p450

‎llvm/docs/ReleaseNotes.md

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and branch and linker relaxation. This can be disabled with ``.option noexact``,
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which is also the default.
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* `-mcpu=xiangshan-kunminghu` was added.
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* `-mcpu=andes-n45` and `-mcpu=andes-nx45` were added.
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Changes to the WebAssembly Backend
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----------------------------------

‎llvm/lib/Target/RISCV/RISCVProcessors.td

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FeatureStdExtZbkb,
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FeatureStdExtZcb,
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FeatureStdExtZcmp]>;
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def ANDES_N45 : RISCVProcessorModel<"andes-n45",
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NoSchedModel,
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[Feature32Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtB]>;
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def ANDES_NX45 : RISCVProcessorModel<"andes-nx45",
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NoSchedModel,
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[Feature64Bit,
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FeatureStdExtI,
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FeatureStdExtZicsr,
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FeatureStdExtZifencei,
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FeatureStdExtM,
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FeatureStdExtA,
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FeatureStdExtF,
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FeatureStdExtD,
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FeatureStdExtC,
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FeatureStdExtB]>;

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