Use getRVVMCOpcode to avoid list all pseduo instruction.

Author: Yeting Kuo

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

@@ -3502,17 +3502,9 @@ bool RISCVDAGToDAGISel::performCombineVMergeAndVOps(SDNode *N) {
     return false;
 
   // This transformation is illegal for viota.m when Mask is not a true mask.
-  switch (True->getMachineOpcode()) {
-  case RISCV::PseudoVIOTA_M_MF8:
-  case RISCV::PseudoVIOTA_M_MF4:
-  case RISCV::PseudoVIOTA_M_MF2:
-  case RISCV::PseudoVIOTA_M_M1:
-  case RISCV::PseudoVIOTA_M_M2:
-  case RISCV::PseudoVIOTA_M_M4:
-  case RISCV::PseudoVIOTA_M_M8:
+  if (RISCV::getRVVMCOpcode(True->getMachineOpcode()) == RISCV::VIOTA_M)
     if (Mask && !usesAllOnesMask(Mask, Glue))
       return false;
-  }
 
   unsigned TrueOpc = True.getMachineOpcode();
   const MCInstrDesc &TrueMCID = TII->get(TrueOpc);