Use modify instead of write for clearing sr1

burrbull · burrbull · commit 89690a8a3ce5 · 2024-12-28T23:15:18.000+03:00
diff --git a/CHANGELOG.md b/CHANGELOG.md
@@ -16,7 +16,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
   Remove `RemapStruct`s. [#462] [#506] [#509]
 - Use independent `Spi` and `SpiSlave` structures instead of `OP` generic [#462]
 - Take `&Clocks` instead of `Clocks` [#498]
-- Temporary replace `stm32f1` with `stm32f1-staging` [#503]
+- Temporary replace `stm32f1` with `stm32f1-staging` v0.17.1 [#503]
 - `Spi` now takes `Option<PIN>` for `SCK`, `MISO`, `MOSI` [#514]
 - move `Qei` mod inside `pwm_input` mod [#516]
 
diff --git a/Cargo.toml b/Cargo.toml
@@ -2,7 +2,10 @@
 edition = "2021"
 rust-version = "1.59"
 
-authors = ["Jorge Aparicio <jorge@japaric.io>", "Daniel Egger <daniel@eggers-club.de>"]
+authors = [
+    "Jorge Aparicio <jorge@japaric.io>",
+    "Daniel Egger <daniel@eggers-club.de>",
+]
 categories = ["embedded", "hardware-support", "no-std"]
 description = "HAL for the STM32F1xx family of microcontrollers"
 keywords = ["arm", "cortex-m", "stm32", "hal"]
@@ -33,7 +36,7 @@ vcell = "0.1.3"
 
 [dependencies.stm32f1]
 package = "stm32f1-staging"
-version = "0.16.0"
+version = "0.17.1"
 features = ["atomics"]
 
 [dependencies.embedded-hal-02]
diff --git a/src/adc.rs b/src/adc.rs
@@ -256,7 +256,7 @@ macro_rules! adc_hal {
 
                 #[inline(always)]
                 pub fn set_external_trigger(&mut self, trigger: crate::pac::$adc::cr2::EXTSEL) {
-                    self.rb.cr2().modify(|_, w| w.extsel().variant(trigger))
+                    self.rb.cr2().modify(|_, w| w.extsel().variant(trigger));
                 }
 
                 fn power_up(&mut self) {
@@ -336,7 +336,7 @@ macro_rules! adc_hal {
                         16 => self.rb.smpr1().modify(|_, w| w.smp16().set(sample_time)),
                         17 => self.rb.smpr1().modify(|_, w| w.smp17().set(sample_time)),
                         _ => unreachable!(),
-                    }
+                    };
                 }
 
                 fn set_regular_sequence (&mut self, channels: &[u8]) {
diff --git a/src/crc.rs b/src/crc.rs
@@ -30,7 +30,7 @@ impl Crc {
     }
 
     pub fn write(&mut self, val: u32) {
-        self.crc.dr().write(|w| w.dr().set(val))
+        self.crc.dr().write(|w| w.dr().set(val));
     }
 
     pub fn reset(&self) {
diff --git a/src/dma.rs b/src/dma.rs
@@ -165,14 +165,14 @@ impl<DMA: DmaExt, const C: u8> Ch<DMA, C> {
         match event {
             Event::HalfTransfer => self.ch().cr().modify(|_, w| w.htie().set_bit()),
             Event::TransferComplete => self.ch().cr().modify(|_, w| w.tcie().set_bit()),
-        }
+        };
     }
 
     pub fn unlisten(&mut self, event: Event) {
         match event {
             Event::HalfTransfer => self.ch().cr().modify(|_, w| w.htie().clear_bit()),
             Event::TransferComplete => self.ch().cr().modify(|_, w| w.tcie().clear_bit()),
-        }
+        };
     }
 
     pub fn ch(&mut self) -> &pac::dma1::CH {
diff --git a/src/gpio.rs b/src/gpio.rs
@@ -532,14 +532,14 @@ impl<const P: char, const N: u8, MODE> Pin<P, N, MODE> {
     fn _set_high(&mut self) {
         // NOTE(unsafe) atomic write to a stateless register
         let gpio = unsafe { &(*gpiox::<P>()) };
-        gpio.bsrr().write(|w| w.bs(N).set_bit())
+        gpio.bsrr().write(|w| w.bs(N).set_bit());
     }
 
     #[inline(always)]
     fn _set_low(&mut self) {
         // NOTE(unsafe) atomic write to a stateless register
         let gpio = unsafe { &(*gpiox::<P>()) };
-        gpio.bsrr().write(|w| w.br(N).set_bit())
+        gpio.bsrr().write(|w| w.br(N).set_bit());
     }
 
     #[inline(always)]
@@ -966,7 +966,7 @@ where
                 } else {
                     w.br(N).set_bit()
                 }
-            })
+            });
         }
 
         match N {
diff --git a/src/i2c.rs b/src/i2c.rs
@@ -271,6 +271,9 @@ impl<I2C: Instance> I2c<I2C> {
 
     /// Generate START condition
     fn send_start(&mut self) {
+        // Clear all pending error bits
+        // NOTE(unsafe): Writing 0 clears the r/w bits and has no effect on the r bits
+        self.i2c.sr1().write(|w| unsafe { w.bits(0) });
         self.i2c.cr1().modify(|_, w| w.start().set_bit());
     }
 
diff --git a/src/rcc.rs b/src/rcc.rs
@@ -213,7 +213,7 @@ impl CFGR {
                 } else {
                     0b010
                 })
-            })
+            });
         }
 
         let rcc = unsafe { &*RCC::ptr() };
diff --git a/src/rtc.rs b/src/rtc.rs
@@ -128,7 +128,7 @@ impl Rtc<RtcClkLse> {
             w.rtcen().set_bit();
             // Set the source of the RTC to LSE
             w.rtcsel().lse()
-        })
+        });
     }
 }
 
@@ -202,7 +202,7 @@ impl Rtc<RtcClkLsi> {
             w.rtcen().set_bit();
             // Set the source of the RTC to LSI
             w.rtcsel().lsi()
-        })
+        });
     }
 }
 
@@ -280,7 +280,7 @@ impl Rtc<RtcClkHseDiv128> {
             w.rtcen().set_bit();
             // Set the source of the RTC to HSE/128
             w.rtcsel().hse()
-        })
+        });
     }
 }
 
@@ -365,22 +365,30 @@ impl<CS> Rtc<CS> {
 
     /// Enables triggering the RTC interrupt every time the RTC counter is increased
     pub fn listen_seconds(&mut self) {
-        self.perform_write(|s| s.regs.crh().modify(|_, w| w.secie().set_bit()))
+        self.perform_write(|s| {
+            s.regs.crh().modify(|_, w| w.secie().set_bit());
+        })
     }
 
     /// Disables the RTC second interrupt
     pub fn unlisten_seconds(&mut self) {
-        self.perform_write(|s| s.regs.crh().modify(|_, w| w.secie().clear_bit()))
+        self.perform_write(|s| {
+            s.regs.crh().modify(|_, w| w.secie().clear_bit());
+        })
     }
 
     /// Clears the RTC second interrupt flag
     pub fn clear_second_flag(&mut self) {
-        self.perform_write(|s| s.regs.crl().modify(|_, w| w.secf().clear_bit()))
+        self.perform_write(|s| {
+            s.regs.crl().modify(|_, w| w.secf().clear_bit());
+        })
     }
 
     /// Clears the RTC alarm interrupt flag
     pub fn clear_alarm_flag(&mut self) {
-        self.perform_write(|s| s.regs.crl().modify(|_, w| w.alrf().clear_bit()))
+        self.perform_write(|s| {
+            s.regs.crl().modify(|_, w| w.alrf().clear_bit());
+        })
     }
 
     /**
diff --git a/src/timer.rs b/src/timer.rs
@@ -325,7 +325,7 @@ macro_rules! hal {
                 }
                 #[inline(always)]
                 unsafe fn set_auto_reload_unchecked(&mut self, arr: u32) {
-                    self.arr().write(|w| w.bits(arr))
+                    self.arr().write(|w| w.bits(arr));
                 }
                 #[inline(always)]
                 fn set_auto_reload(&mut self, arr: u32) -> Result<(), Error> {
@@ -445,7 +445,7 @@ macro_rules! with_pwm {
                 let tim = unsafe { &*<$TIM>::ptr() };
                 #[allow(unused_unsafe)]
                 if channel < Self::CH_NUMBER {
-                    tim.ccr(channel as usize).write(|w| unsafe { w.bits(value) })
+                    tim.ccr(channel as usize).write(|w| unsafe { w.bits(value) });
                 }
             }
 
@@ -493,7 +493,7 @@ macro_rules! with_pwm {
                 let tim = unsafe { &*<$TIM>::ptr() };
                 #[allow(unused_unsafe)]
                 if channel < Self::CH_NUMBER {
-                    tim.ccr(channel as usize).write(|w| unsafe { w.bits(value) })
+                    tim.ccr(channel as usize).write(|w| unsafe { w.bits(value) });
                 }
             }
 
@@ -539,7 +539,7 @@ macro_rules! with_pwm {
             #[inline(always)]
             fn set_cc_value(channel: u8, value: u32) {
                 let tim = unsafe { &*<$TIM>::ptr() };
-                tim.ccr(channel as usize).write(|w| unsafe { w.bits(value) })
+                tim.ccr(channel as usize).write(|w| unsafe { w.bits(value) });
             }
 
             #[inline(always)]

Original file line number	Diff line number	Diff line change
`@@ -256,7 +256,7 @@ macro_rules! adc_hal {`
`256`	`256`
`257`	`257`	`#[inline(always)]`
`258`	`258`	`pub fn set_external_trigger(&mut self, trigger: crate::pac::$adc::cr2::EXTSEL) {`
`259`		`- self.rb.cr2().modify(\|_, w\| w.extsel().variant(trigger))`
	`259`	`+ self.rb.cr2().modify(\|_, w\| w.extsel().variant(trigger));`
`260`	`260`	`}`
`261`	`261`
`262`	`262`	`fn power_up(&mut self) {`
`@@ -336,7 +336,7 @@ macro_rules! adc_hal {`
`336`	`336`	`16 => self.rb.smpr1().modify(\|_, w\| w.smp16().set(sample_time)),`
`337`	`337`	`17 => self.rb.smpr1().modify(\|_, w\| w.smp17().set(sample_time)),`
`338`	`338`	`_ => unreachable!(),`
`339`		`- }`
	`339`	`+ };`
`340`	`340`	`}`
`341`	`341`
`342`	`342`	`fn set_regular_sequence (&mut self, channels: &[u8]) {`
Original file line number	Diff line number	Diff line change
`@@ -30,7 +30,7 @@ impl Crc {`
`30`	`30`	`}`
`31`	`31`
`32`	`32`	`pub fn write(&mut self, val: u32) {`
`33`		`- self.crc.dr().write(\|w\| w.dr().set(val))`
	`33`	`+ self.crc.dr().write(\|w\| w.dr().set(val));`
`34`	`34`	`}`
`35`	`35`
`36`	`36`	`pub fn reset(&self) {`
Original file line number	Diff line number	Diff line change
`@@ -532,14 +532,14 @@ impl<const P: char, const N: u8, MODE> Pin<P, N, MODE> {`
`532`	`532`	`fn _set_high(&mut self) {`
`533`	`533`	`// NOTE(unsafe) atomic write to a stateless register`
`534`	`534`	`let gpio = unsafe { &(*gpiox::<P>()) };`
`535`		`- gpio.bsrr().write(\|w\| w.bs(N).set_bit())`
	`535`	`+ gpio.bsrr().write(\|w\| w.bs(N).set_bit());`
`536`	`536`	`}`
`537`	`537`
`538`	`538`	`#[inline(always)]`
`539`	`539`	`fn _set_low(&mut self) {`
`540`	`540`	`// NOTE(unsafe) atomic write to a stateless register`
`541`	`541`	`let gpio = unsafe { &(*gpiox::<P>()) };`
`542`		`- gpio.bsrr().write(\|w\| w.br(N).set_bit())`
	`542`	`+ gpio.bsrr().write(\|w\| w.br(N).set_bit());`
`543`	`543`	`}`
`544`	`544`
`545`	`545`	`#[inline(always)]`
`@@ -966,7 +966,7 @@ where`
`966`	`966`	`} else {`
`967`	`967`	`w.br(N).set_bit()`
`968`	`968`	`}`
`969`		`- })`
	`969`	`+ });`
`970`	`970`	`}`
`971`	`971`
`972`	`972`	`match N {`
Original file line number	Diff line number	Diff line change
`@@ -271,6 +271,9 @@ impl<I2C: Instance> I2c<I2C> {`
`271`	`271`
`272`	`272`	`/// Generate START condition`
`273`	`273`	`fn send_start(&mut self) {`
	`274`	`+ // Clear all pending error bits`
	`275`	`+ // NOTE(unsafe): Writing 0 clears the r/w bits and has no effect on the r bits`
	`276`	`+ self.i2c.sr1().write(\|w\| unsafe { w.bits(0) });`
`274`	`277`	`self.i2c.cr1().modify(\|_, w\| w.start().set_bit());`
`275`	`278`	`}`
`276`	`279`
Original file line number	Diff line number	Diff line change
`@@ -213,7 +213,7 @@ impl CFGR {`
`213`	`213`	`} else {`
`214`	`214`	`0b010`
`215`	`215`	`})`
`216`		`- })`
	`216`	`+ });`
`217`	`217`	`}`
`218`	`218`
`219`	`219`	`let rcc = unsafe { &*RCC::ptr() };`
Original file line number	Diff line number	Diff line change
`@@ -128,7 +128,7 @@ impl Rtc<RtcClkLse> {`
`128`	`128`	`w.rtcen().set_bit();`
`129`	`129`	`// Set the source of the RTC to LSE`
`130`	`130`	`w.rtcsel().lse()`
`131`		`- })`
	`131`	`+ });`
`132`	`132`	`}`
`133`	`133`	`}`
`134`	`134`
`@@ -202,7 +202,7 @@ impl Rtc<RtcClkLsi> {`
`202`	`202`	`w.rtcen().set_bit();`
`203`	`203`	`// Set the source of the RTC to LSI`
`204`	`204`	`w.rtcsel().lsi()`
`205`		`- })`
	`205`	`+ });`
`206`	`206`	`}`
`207`	`207`	`}`
`208`	`208`
`@@ -280,7 +280,7 @@ impl Rtc<RtcClkHseDiv128> {`
`280`	`280`	`w.rtcen().set_bit();`
`281`	`281`	`// Set the source of the RTC to HSE/128`
`282`	`282`	`w.rtcsel().hse()`
`283`		`- })`
	`283`	`+ });`
`284`	`284`	`}`
`285`	`285`	`}`
`286`	`286`
`@@ -365,22 +365,30 @@ impl<CS> Rtc<CS> {`
`365`	`365`
`366`	`366`	`/// Enables triggering the RTC interrupt every time the RTC counter is increased`
`367`	`367`	`pub fn listen_seconds(&mut self) {`
`368`		`- self.perform_write(\|s\| s.regs.crh().modify(\|_, w\| w.secie().set_bit()))`
	`368`	`+ self.perform_write(\|s\| {`
	`369`	`+ s.regs.crh().modify(\|_, w\| w.secie().set_bit());`
	`370`	`+ })`
`369`	`371`	`}`
`370`	`372`
`371`	`373`	`/// Disables the RTC second interrupt`
`372`	`374`	`pub fn unlisten_seconds(&mut self) {`
`373`		`- self.perform_write(\|s\| s.regs.crh().modify(\|_, w\| w.secie().clear_bit()))`
	`375`	`+ self.perform_write(\|s\| {`
	`376`	`+ s.regs.crh().modify(\|_, w\| w.secie().clear_bit());`
	`377`	`+ })`
`374`	`378`	`}`
`375`	`379`
`376`	`380`	`/// Clears the RTC second interrupt flag`
`377`	`381`	`pub fn clear_second_flag(&mut self) {`
`378`		`- self.perform_write(\|s\| s.regs.crl().modify(\|_, w\| w.secf().clear_bit()))`
	`382`	`+ self.perform_write(\|s\| {`
	`383`	`+ s.regs.crl().modify(\|_, w\| w.secf().clear_bit());`
	`384`	`+ })`
`379`	`385`	`}`
`380`	`386`
`381`	`387`	`/// Clears the RTC alarm interrupt flag`
`382`	`388`	`pub fn clear_alarm_flag(&mut self) {`
`383`		`- self.perform_write(\|s\| s.regs.crl().modify(\|_, w\| w.alrf().clear_bit()))`
	`389`	`+ self.perform_write(\|s\| {`
	`390`	`+ s.regs.crl().modify(\|_, w\| w.alrf().clear_bit());`
	`391`	`+ })`
`384`	`392`	`}`
`385`	`393`
`386`	`394`	`/**`
Original file line number	Diff line number	Diff line change
`@@ -325,7 +325,7 @@ macro_rules! hal {`
`325`	`325`	`}`
`326`	`326`	`#[inline(always)]`
`327`	`327`	`unsafe fn set_auto_reload_unchecked(&mut self, arr: u32) {`
`328`		`- self.arr().write(\|w\| w.bits(arr))`
	`328`	`+ self.arr().write(\|w\| w.bits(arr));`
`329`	`329`	`}`
`330`	`330`	`#[inline(always)]`
`331`	`331`	`fn set_auto_reload(&mut self, arr: u32) -> Result<(), Error> {`
`@@ -445,7 +445,7 @@ macro_rules! with_pwm {`
`445`	`445`	`let tim = unsafe { &*<$TIM>::ptr() };`
`446`	`446`	`#[allow(unused_unsafe)]`
`447`	`447`	`if channel < Self::CH_NUMBER {`
`448`		`- tim.ccr(channel as usize).write(\|w\| unsafe { w.bits(value) })`
	`448`	`+ tim.ccr(channel as usize).write(\|w\| unsafe { w.bits(value) });`
`449`	`449`	`}`
`450`	`450`	`}`
`451`	`451`
`@@ -493,7 +493,7 @@ macro_rules! with_pwm {`
`493`	`493`	`let tim = unsafe { &*<$TIM>::ptr() };`
`494`	`494`	`#[allow(unused_unsafe)]`
`495`	`495`	`if channel < Self::CH_NUMBER {`
`496`		`- tim.ccr(channel as usize).write(\|w\| unsafe { w.bits(value) })`
	`496`	`+ tim.ccr(channel as usize).write(\|w\| unsafe { w.bits(value) });`
`497`	`497`	`}`
`498`	`498`	`}`
`499`	`499`
`@@ -539,7 +539,7 @@ macro_rules! with_pwm {`
`539`	`539`	`#[inline(always)]`
`540`	`540`	`fn set_cc_value(channel: u8, value: u32) {`
`541`	`541`	`let tim = unsafe { &*<$TIM>::ptr() };`
`542`		`- tim.ccr(channel as usize).write(\|w\| unsafe { w.bits(value) })`
	`542`	`+ tim.ccr(channel as usize).write(\|w\| unsafe { w.bits(value) });`
`543`	`543`	`}`
`544`	`544`
`545`	`545`	`#[inline(always)]`