@@ -24,7 +24,42 @@ public class Arm64InstructionFactoryTests_LUTI4_Advsimd
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[ TestMethod ]
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public void Test_LUTI4_asimdtbl_l5_0 ( )
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{
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- Assert . Inconclusive ( "Not handled LUTI4_asimdtbl_l5 - LUTI4 Vd.16B, {Vn.16B}, Vm[index]" ) ;
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+
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+ {
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+ var raw = LUTI4 ( V0 . T_16B , V1 . T_16B . Group1 ( ) , V2 [ 1 ] ) ;
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+ var instruction = Arm64Instruction . Decode ( raw ) ;
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+ Assert . AreEqual ( Arm64InstructionId . LUTI4_asimdtbl_l5 , instruction . Id ) ;
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+ Assert . AreEqual ( Arm64Mnemonic . LUTI4 , instruction . Mnemonic ) ;
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+ var asm = instruction . ToString ( "H" , null ) ;
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+ Assert . AreEqual ( "LUTI4 V0.16B, { V1.16B }, V2[1]" , asm ) ;
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+ }
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+
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+ {
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+ var raw = LUTI4 ( V30 . T_16B , V1 . T_16B . Group1 ( ) , V2 [ 1 ] ) ;
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+ var instruction = Arm64Instruction . Decode ( raw ) ;
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+ Assert . AreEqual ( Arm64InstructionId . LUTI4_asimdtbl_l5 , instruction . Id ) ;
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+ Assert . AreEqual ( Arm64Mnemonic . LUTI4 , instruction . Mnemonic ) ;
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+ var asm = instruction . ToString ( "H" , null ) ;
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+ Assert . AreEqual ( "LUTI4 V30.16B, { V1.16B }, V2[1]" , asm ) ;
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+ }
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+
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+ {
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+ var raw = LUTI4 ( V0 . T_16B , V31 . T_16B . Group1 ( ) , V2 [ 1 ] ) ;
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+ var instruction = Arm64Instruction . Decode ( raw ) ;
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+ Assert . AreEqual ( Arm64InstructionId . LUTI4_asimdtbl_l5 , instruction . Id ) ;
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+ Assert . AreEqual ( Arm64Mnemonic . LUTI4 , instruction . Mnemonic ) ;
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+ var asm = instruction . ToString ( "H" , null ) ;
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+ Assert . AreEqual ( "LUTI4 V0.16B, { V31.16B }, V2[1]" , asm ) ;
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+ }
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+
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+ {
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+ var raw = LUTI4 ( V30 . T_16B , V31 . T_16B . Group1 ( ) , V2 [ 1 ] ) ;
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+ var instruction = Arm64Instruction . Decode ( raw ) ;
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+ Assert . AreEqual ( Arm64InstructionId . LUTI4_asimdtbl_l5 , instruction . Id ) ;
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+ Assert . AreEqual ( Arm64Mnemonic . LUTI4 , instruction . Mnemonic ) ;
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+ var asm = instruction . ToString ( "H" , null ) ;
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+ Assert . AreEqual ( "LUTI4 V30.16B, { V31.16B }, V2[1]" , asm ) ;
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+ }
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}
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/// <summary>
@@ -33,6 +68,41 @@ public void Test_LUTI4_asimdtbl_l5_0()
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[ TestMethod ]
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public void Test_LUTI4_asimdtbl_l7_1 ( )
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{
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- Assert . Inconclusive ( "Not handled LUTI4_asimdtbl_l7 - LUTI4 Vd.8H, {Vn1.8H, Vn2.8H}, Vm[index]" ) ;
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+
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+ {
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+ var raw = LUTI4 ( V0 . T_8H , V1 . T_8H . Group2 ( ) , V2 [ 1 ] ) ;
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+ var instruction = Arm64Instruction . Decode ( raw ) ;
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+ Assert . AreEqual ( Arm64InstructionId . LUTI4_asimdtbl_l7 , instruction . Id ) ;
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+ Assert . AreEqual ( Arm64Mnemonic . LUTI4 , instruction . Mnemonic ) ;
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+ var asm = instruction . ToString ( "H" , null ) ;
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+ Assert . AreEqual ( "LUTI4 V0.8H, { V1.8H, V2.8H }, V2[1]" , asm ) ;
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+ }
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+
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+ {
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+ var raw = LUTI4 ( V30 . T_8H , V1 . T_8H . Group2 ( ) , V2 [ 1 ] ) ;
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+ var instruction = Arm64Instruction . Decode ( raw ) ;
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+ Assert . AreEqual ( Arm64InstructionId . LUTI4_asimdtbl_l7 , instruction . Id ) ;
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+ Assert . AreEqual ( Arm64Mnemonic . LUTI4 , instruction . Mnemonic ) ;
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+ var asm = instruction . ToString ( "H" , null ) ;
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+ Assert . AreEqual ( "LUTI4 V30.8H, { V1.8H, V2.8H }, V2[1]" , asm ) ;
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+ }
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+
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+ {
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+ var raw = LUTI4 ( V0 . T_8H , V31 . T_8H . Group2 ( ) , V2 [ 1 ] ) ;
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+ var instruction = Arm64Instruction . Decode ( raw ) ;
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+ Assert . AreEqual ( Arm64InstructionId . LUTI4_asimdtbl_l7 , instruction . Id ) ;
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+ Assert . AreEqual ( Arm64Mnemonic . LUTI4 , instruction . Mnemonic ) ;
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+ var asm = instruction . ToString ( "H" , null ) ;
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+ Assert . AreEqual ( "LUTI4 V0.8H, { V31.8H, V0.8H }, V2[1]" , asm ) ;
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+ }
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+
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+ {
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+ var raw = LUTI4 ( V30 . T_8H , V31 . T_8H . Group2 ( ) , V2 [ 1 ] ) ;
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+ var instruction = Arm64Instruction . Decode ( raw ) ;
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+ Assert . AreEqual ( Arm64InstructionId . LUTI4_asimdtbl_l7 , instruction . Id ) ;
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+ Assert . AreEqual ( Arm64Mnemonic . LUTI4 , instruction . Mnemonic ) ;
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+ var asm = instruction . ToString ( "H" , null ) ;
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+ Assert . AreEqual ( "LUTI4 V30.8H, { V31.8H, V0.8H }, V2[1]" , asm ) ;
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+ }
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}
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}
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