2025.1

fpga-hls-examples 2025.1

Changes since last release (v2024.1)

• Added SHLS examples to demonstrate Error Correction Code and Automatic On-Chip Instrumentation functionality
• (Canny RISC-V) Added an example demonstrating how to design an SHLS module with input and output FIFOs in a RISC-V environment
• Updated source code and documentation for trainings to compile with Libero/SmartHLS 2025.1
• Included pre-generated .job files for trainings compiled with Libero 2025.1
• Moved LFS files to Release Assets

Known Issues:

• For the auto instrumentation example:
  • If run using Windows, you may see the error "Error: can't read "merged_file": no such variable". To fix this, open C:\Microchip\Libero_SoC_2025.1\SmartHLS\SmartHLS\examples\scripts\utils\instrument\update_vcd.tcl. On line 198, change "$merged_file" to "$vcdFile".
  • If run on Windows or Linux, Modelsim may display the error message saying "....clken" signals were not found. To solve this issue, go to line 257 of C:\Microchip\Libero_SoC_2025.1\SmartHLS\SmartHLS\lib\python\instrumentation\read_vcd.py and change "clk" to "clk$".
  • These issues will be addressed in the next release of Libero.

2025.1

fpga-hls-examples 2025.1

Changes since last release (v2024.1)

• Updated source code and documentation for trainings to compile with Libero/SmartHLS 2025.1.
• Included pre-generated .job files for trainings compiled with Libero 2025.1.
• Included the LFS files as part of precompiled libraries in Assets

2023.2

• Updated Training documents for SmartHLS 2023.2
• Added examples of the SmartHLS dataflow feature into Trainings 1 and 2
• Added a 4th training covering the SmartHLS PolarFire SoC flow. Targets either the Icicle kit reference design or a custom design.