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Enhance CPU manager with L3 cache aware #2621

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@hustcat

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@hustcat

Enhancement Description

  • One-line enhancement description (can be used as a release note):
    Some CPUs, such as AMD Rome, each CPU package(socket) have multiple L3 caches. When allocating CPUs, L3 cache should be considered.

  • Kubernetes Enhancement Proposal:

  • Discussion Link:

  • Primary contact (assignee): @hustcat @ranchothu

  • Responsible SIGs: node

  • Enhancement target (which target equals to which milestone):

    • Alpha release target (x.y): v1.22
    • Beta release target (x.y):
    • Stable release target (x.y):
  • Alpha

    • KEP (k/enhancements) update PR(s):
    • Code (k/k) update PR(s):
    • Docs (k/website) update PR(s):

Please keep this description up to date. This will help the Enhancement Team to track the evolution of the enhancement efficiently.

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lifecycle/rottenDenotes an issue or PR that has aged beyond stale and will be auto-closed.sig/nodeCategorizes an issue or PR as relevant to SIG Node.

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