This repository consists of four projects or "labs" which were developed for the needs of the course "Digital Systems Lab". This course is part of the undergraduate studies of University of Thessally - ECE Department, which is located in Volos, Greece.
Link to the Department's official site: https://www.e-ce.uth.gr/?lang=en
My name is Panagiotis Anastasiadis and these projects were assigned to me during the time of my undergraduate studies and the enrollment of course "Digital Systems Lab".
If there are any sights of bad practices or ambiguities regarding the file structure, code quality, the general development of the projects or the entire repo management, please mind that this work attempt to strictly focus on the course nature and fit the requirements for the assignments set by it. Also, consider the lack of expertise or experience that comes along during the time of undergraduate studies.
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These projects aimed to give a good understanding for both the digital systems fundamentals and the FPGA programming concept.
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All of them are written in Verilog language and are tested and designed to run on Xilinx Spartan-3 and Spartan-3E FPGA boards. The tool that was used during the deveplopement, is the ISE Design Suite 14.7 from Xilinx.
Implementation of a LED Controller that drives the 7-Segment display on Spartan-3 FPGA board and displays certain messages.
Implementation of a system cirquit that transfers data by using the UART(Universal Asynchronous Receiver-Transmitter) protocol and consists of a UART transmitter and a UART receiver.
Implementation of a VGA Controller that drives a monitor with 640x480 resolution and refresh rate of 60 MHz. A static picture that can be displayed on the monitor, is stored inside a video ram, which is also implemented.
Implementation of a LCD Driver that drives the LCD on the Spartan 3E board and displays a message, including a blinking cursor. This lab emphasizes on FSMs, meaning that the project has an extended use of them.