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drm/v3d: Fix GPU reset issues on the Raspberry Pi 5 for 6.14 #6715

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Merged
merged 9 commits into from
Mar 12, 2025
Merged

drm/v3d: Fix GPU reset issues on the Raspberry Pi 5 for 6.14 #6715

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3b4e923
drm/v3d: Add clock handling
lategoodbye Feb 1, 2025
83c9aea
drm/v3d: Don't run jobs that have errors flagged in its fence
mairacanal Mar 11, 2025
bdac343
drm/v3d: Set job pointer to NULL when the job's fence has an error
mairacanal Mar 11, 2025
0050c36
drm/v3d: Associate a V3D tech revision to all supported devices
mairacanal Mar 11, 2025
10a1a41
dt-bindings: gpu: v3d: Add per-compatible register restrictions
mairacanal Mar 11, 2025
4854017
dt-bindings: gpu: v3d: Add SMS register to BCM2712 compatible
mairacanal Mar 11, 2025
b3db5bd
drm/v3d: Use V3D_SMS registers for power on/off and reset on V3D 7.x
mairacanal Mar 11, 2025
b6a7aa7
dt-bindings: gpu: Add V3D driver maintainer as DT maintainer
mairacanal Mar 11, 2025
c956bd1
dts: bcm2712: Add V3D_SMS register
mairacanal Feb 28, 2025
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77 changes: 66 additions & 11 deletions Documentation/devicetree/bindings/gpu/brcm,bcm-v3d.yaml
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Original file line number Diff line number Diff line change
Expand Up @@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Broadcom V3D GPU

maintainers:
- Eric Anholt <[email protected]>
- Maíra Canal <[email protected]>
- Nicolas Saenz Julienne <[email protected]>

properties:
Expand All @@ -23,20 +23,12 @@ properties:
- brcm,7278-v3d

reg:
items:
- description: hub register (required)
- description: core0 register (required)
- description: GCA cache controller register (if GCA controller present)
- description: bridge register (if no external reset controller)
minItems: 2
maxItems: 4

reg-names:
items:
- const: hub
- const: core0
- enum: [ bridge, gca ]
- enum: [ bridge, gca ]
minItems: 2
maxItems: 4

interrupts:
items:
Expand All @@ -59,6 +51,69 @@ required:
- reg-names
- interrupts

allOf:
- if:
properties:
compatible:
contains:
enum:
- brcm,2711-v3d
- brcm,7278-v3d
then:
properties:
reg:
items:
- description: hub register (required)
- description: core0 register (required)
- description: bridge register (if no external reset controller)
reg-names:
items:
- const: hub
- const: core0
- const: bridge
- if:
properties:
compatible:
contains:
const: brcm,2712-v3d
then:
properties:
reg:
items:
- description: hub register (required)
- description: core0 register (required)
- description: SMS register (required)
- description: bridge register (if no external reset controller)
minItems: 3
reg-names:
items:
- const: hub
- const: core0
- const: sms
- const: bridge
minItems: 3
- if:
properties:
compatible:
contains:
const: brcm,7268-v3d
then:
properties:
reg:
items:
- description: hub register (required)
- description: core0 register (required)
- description: GCA cache controller register (required)
- description: bridge register (if no external reset controller)
minItems: 3
reg-names:
items:
- const: hub
- const: core0
- enum: [ bridge, gca ]
- enum: [ bridge, gca ]
minItems: 3

additionalProperties: false

examples:
Expand Down
5 changes: 3 additions & 2 deletions arch/arm64/boot/dts/broadcom/bcm2712-ds.dtsi
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Original file line number Diff line number Diff line change
Expand Up @@ -409,8 +409,9 @@
v3d: v3d@2000000 {
compatible = "brcm,2712-v3d";
reg = <0x10 0x02000000 0x0 0x4000>,
<0x10 0x02008000 0x0 0x6000>;
reg-names = "hub", "core0";
<0x10 0x02008000 0x0 0x6000>,
<0x10 0x02030800 0x0 0x0700>;
reg-names = "hub", "core0", "sms";

power-domains = <&pm BCM2835_POWER_DOMAIN_GRAFX_V3D>;
resets = <&pm BCM2835_RESET_V3D>;
Expand Down
126 changes: 63 additions & 63 deletions drivers/gpu/drm/v3d/v3d_debugfs.c
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Original file line number Diff line number Diff line change
Expand Up @@ -21,74 +21,74 @@ struct v3d_reg_def {
};

static const struct v3d_reg_def v3d_hub_reg_defs[] = {
REGDEF(33, 42, V3D_HUB_AXICFG),
REGDEF(33, 71, V3D_HUB_UIFCFG),
REGDEF(33, 71, V3D_HUB_IDENT0),
REGDEF(33, 71, V3D_HUB_IDENT1),
REGDEF(33, 71, V3D_HUB_IDENT2),
REGDEF(33, 71, V3D_HUB_IDENT3),
REGDEF(33, 71, V3D_HUB_INT_STS),
REGDEF(33, 71, V3D_HUB_INT_MSK_STS),

REGDEF(33, 71, V3D_MMU_CTL),
REGDEF(33, 71, V3D_MMU_VIO_ADDR),
REGDEF(33, 71, V3D_MMU_VIO_ID),
REGDEF(33, 71, V3D_MMU_DEBUG_INFO),

REGDEF(71, 71, V3D_GMP_STATUS(71)),
REGDEF(71, 71, V3D_GMP_CFG(71)),
REGDEF(71, 71, V3D_GMP_VIO_ADDR(71)),
REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_HUB_AXICFG),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_UIFCFG),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT0),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT1),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT2),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_IDENT3),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_INT_STS),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_HUB_INT_MSK_STS),

REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_CTL),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_VIO_ADDR),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_VIO_ID),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_MMU_DEBUG_INFO),

REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_GMP_STATUS(71)),
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_GMP_CFG(71)),
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_GMP_VIO_ADDR(71)),
};

static const struct v3d_reg_def v3d_gca_reg_defs[] = {
REGDEF(33, 33, V3D_GCA_SAFE_SHUTDOWN),
REGDEF(33, 33, V3D_GCA_SAFE_SHUTDOWN_ACK),
REGDEF(V3D_GEN_33, V3D_GEN_33, V3D_GCA_SAFE_SHUTDOWN),
REGDEF(V3D_GEN_33, V3D_GEN_33, V3D_GCA_SAFE_SHUTDOWN_ACK),
};

static const struct v3d_reg_def v3d_core_reg_defs[] = {
REGDEF(33, 71, V3D_CTL_IDENT0),
REGDEF(33, 71, V3D_CTL_IDENT1),
REGDEF(33, 71, V3D_CTL_IDENT2),
REGDEF(33, 71, V3D_CTL_MISCCFG),
REGDEF(33, 71, V3D_CTL_INT_STS),
REGDEF(33, 71, V3D_CTL_INT_MSK_STS),
REGDEF(33, 71, V3D_CLE_CT0CS),
REGDEF(33, 71, V3D_CLE_CT0CA),
REGDEF(33, 71, V3D_CLE_CT0EA),
REGDEF(33, 71, V3D_CLE_CT1CS),
REGDEF(33, 71, V3D_CLE_CT1CA),
REGDEF(33, 71, V3D_CLE_CT1EA),

REGDEF(33, 71, V3D_PTB_BPCA),
REGDEF(33, 71, V3D_PTB_BPCS),

REGDEF(33, 42, V3D_GMP_STATUS(33)),
REGDEF(33, 42, V3D_GMP_CFG(33)),
REGDEF(33, 42, V3D_GMP_VIO_ADDR(33)),

REGDEF(33, 71, V3D_ERR_FDBGO),
REGDEF(33, 71, V3D_ERR_FDBGB),
REGDEF(33, 71, V3D_ERR_FDBGS),
REGDEF(33, 71, V3D_ERR_STAT),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_IDENT0),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_IDENT1),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_IDENT2),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_MISCCFG),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_INT_STS),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CTL_INT_MSK_STS),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT0CS),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT0CA),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT0EA),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT1CS),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT1CA),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_CLE_CT1EA),

REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_PTB_BPCA),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_PTB_BPCS),

REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_GMP_STATUS(33)),
REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_GMP_CFG(33)),
REGDEF(V3D_GEN_33, V3D_GEN_42, V3D_GMP_VIO_ADDR(33)),

REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_FDBGO),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_FDBGB),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_FDBGS),
REGDEF(V3D_GEN_33, V3D_GEN_71, V3D_ERR_STAT),
};

static const struct v3d_reg_def v3d_csd_reg_defs[] = {
REGDEF(41, 71, V3D_CSD_STATUS),
REGDEF(41, 42, V3D_CSD_CURRENT_CFG0(41)),
REGDEF(41, 42, V3D_CSD_CURRENT_CFG1(41)),
REGDEF(41, 42, V3D_CSD_CURRENT_CFG2(41)),
REGDEF(41, 42, V3D_CSD_CURRENT_CFG3(41)),
REGDEF(41, 42, V3D_CSD_CURRENT_CFG4(41)),
REGDEF(41, 42, V3D_CSD_CURRENT_CFG5(41)),
REGDEF(41, 42, V3D_CSD_CURRENT_CFG6(41)),
REGDEF(71, 71, V3D_CSD_CURRENT_CFG0(71)),
REGDEF(71, 71, V3D_CSD_CURRENT_CFG1(71)),
REGDEF(71, 71, V3D_CSD_CURRENT_CFG2(71)),
REGDEF(71, 71, V3D_CSD_CURRENT_CFG3(71)),
REGDEF(71, 71, V3D_CSD_CURRENT_CFG4(71)),
REGDEF(71, 71, V3D_CSD_CURRENT_CFG5(71)),
REGDEF(71, 71, V3D_CSD_CURRENT_CFG6(71)),
REGDEF(71, 71, V3D_V7_CSD_CURRENT_CFG7),
REGDEF(V3D_GEN_41, V3D_GEN_71, V3D_CSD_STATUS),
REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG0(41)),
REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG1(41)),
REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG2(41)),
REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG3(41)),
REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG4(41)),
REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG5(41)),
REGDEF(V3D_GEN_41, V3D_GEN_42, V3D_CSD_CURRENT_CFG6(41)),
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG0(71)),
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG1(71)),
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG2(71)),
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG3(71)),
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG4(71)),
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG5(71)),
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_CSD_CURRENT_CFG6(71)),
REGDEF(V3D_GEN_71, V3D_GEN_71, V3D_V7_CSD_CURRENT_CFG7),
};

static int v3d_v3d_debugfs_regs(struct seq_file *m, void *unused)
Expand Down Expand Up @@ -164,7 +164,7 @@ static int v3d_v3d_debugfs_ident(struct seq_file *m, void *unused)
str_yes_no(ident2 & V3D_HUB_IDENT2_WITH_MMU));
seq_printf(m, "TFU: %s\n",
str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TFU));
if (v3d->ver <= 42) {
if (v3d->ver <= V3D_GEN_42) {
seq_printf(m, "TSY: %s\n",
str_yes_no(ident1 & V3D_HUB_IDENT1_WITH_TSY));
}
Expand Down Expand Up @@ -196,11 +196,11 @@ static int v3d_v3d_debugfs_ident(struct seq_file *m, void *unused)
seq_printf(m, " QPUs: %d\n", nslc * qups);
seq_printf(m, " Semaphores: %d\n",
V3D_GET_FIELD(ident1, V3D_IDENT1_NSEM));
if (v3d->ver <= 42) {
if (v3d->ver <= V3D_GEN_42) {
seq_printf(m, " BCG int: %d\n",
(ident2 & V3D_IDENT2_BCG_INT) != 0);
}
if (v3d->ver < 40) {
if (v3d->ver < V3D_GEN_41) {
seq_printf(m, " Override TMU: %d\n",
(misccfg & V3D_MISCCFG_OVRTMUOUT) != 0);
}
Expand Down Expand Up @@ -234,7 +234,7 @@ static int v3d_measure_clock(struct seq_file *m, void *unused)
int core = 0;
int measure_ms = 1000;

if (v3d->ver >= 40) {
if (v3d->ver >= V3D_GEN_41) {
int cycle_count_reg = V3D_PCTR_CYCLE_COUNT(v3d->ver);
V3D_CORE_WRITE(core, V3D_V4_PCTR_0_SRC_0_3,
V3D_SET_FIELD_VER(cycle_count_reg,
Expand Down
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