`riscv`: Add missing CSR's

[dvc94ch]

• mpu
• mdelet /mideleg
• perf counters
• senvcfg
• scontext
• mconfigptr
• mtinst
• mtval2
• Machine Configuration registers
• Machine Non-Maskable Interrupt Handling registers
• Machine Counter Setup registers
• Machine Debug/Trace registers
• Machine Dabug Mode registers

[bjorn3]

The Advanced Interrupt Architecture specification defines a bunch more CSR's:

• miselect
• mireg
• mtopei
• mtopi
• mvien
• mvip
• siselect
• sireg
• stopei
• stopi
• hvien
• hvictl
• hviprio1
• hviprio2
• vsiselect
• vsireg
• vstopei
• vstopi

[romancardenas]

Good point!

Maybe it would be a better idea to open a new issue where we can discuss how to implement the AIA in our ecosystem

[bjorn3]

Opened #226