Popular repositories Loading

1. svinst svinst Public

   Determines the modules declared and instantiated in a SystemVerilog file

   Rust 46 5

2. svreal svreal Public

   Synthesizable real number library in SystemVerilog, supporting both fixed- and floating-point formats

   SystemVerilog 45 9

3. msdsl msdsl Public

   Automatic generation of real number models from analog circuits

   Python 41 12

4. anasymod anasymod Public

   A framework for FPGA emulation of mixed-signal systems

   Python 36 10

5. pysvinst pysvinst Public

   Python library for parsing module definitions and instantiations from SystemVerilog files

   Python 23 6

6. sky130-hello-world sky130-hello-world Public

   Minimal SKY130 example with self-checking LVS, DRC, and PEX

   Shell 23 9